AMD Am186 CC User Manual page 139

Table 8-2 DMA Controller Register Summary (Continued)
Register
Offset
Mnemonic
10Ah GD0DSTH
10Ch GD0TC
110h GD1CON0
112h GD1CON1
114h GD1SRCL
116h GD1SRCH
118h GD1DSTL
11Ah GD1DSTH
11Ch GD1TC
120h GD2CON0
122h GD2CON1
124h GD2SRCL
126h GD2SRCH
128h GD2DSTL
12Ah GD2DSTH
12Ch GD2TC
130h GD3CON0
132h GD3CON1
134h GD3SRCL
136h GD3SRCH
138h GD3DSTL
13Ah GD3DSTH
13Ch GD3TC
DMA Controller
Register Name
General-Purpose DMA0 Destination
Address High
General-Purpose DMA0 Transfer Count
General-Purpose DMA1 Control 0
General-Purpose DMA1 Control 1
General-Purpose DMA1 Source
Address Low
General-Purpose DMA1 Source
Address High
General-Purpose DMA1 Destination
Address Low
General-Purpose DMA1 Destination
Address High
General-Purpose DMA1 Transfer Count
General-Purpose DMA2 Control 0
General-Purpose DMA2 Control 1
General-Purpose DMA2 Source
Address Low
General-Purpose DMA2 Source
Address High
General-Purpose DMA2 Destination
Address Low
General-Purpose DMA2 Destination
Address High
General-Purpose DMA2 Transfer Count
General-Purpose DMA3 Control 0
General-Purpose DMA3 Control 1
General-Purpose DMA3 Source
Address Low
General-Purpose DMA3 Source
Address High
General-Purpose DMA3 Destination
Address Low
General-Purpose DMA3 Destination
Address High
General-Purpose DMA3 Transfer Count
Am186™CC/CH/CU Microcontrollers User's Manual
Description
Four bits of this register [19–16], combined
with the 16 bits of the low register, produce a
20-bit destination address for general-purpose
DMA Channel 0.
Sets the transfer count (the number of DMA
transfers to be performed) for general-purpose
DMA Channel 0.
Behaves the same as General-Purpose DMA0
registers, but for DMA Channel 1.
Behaves the same as General-Purpose DMA0
registers, but for DMA Channel 2.
Behaves the same as General-Purpose DMA0
registers, but for DMA Channel 3.
8-5