AMD Am186 CC User Manual page 360

basic-rate GCI, 16-10
baud rate
detection
description, 13-16
enhancement, 13-18
error, 13-17
procedure, 13-7
range, 13-17
programming, 13-15
setting, 13-6
table, UART, 13-15
BEPBUFS register, 18-9
BEPCTL register, 18-9
BEPDAT register, 18-9
BEPDEF1 register, 18-9
BEPDEF2 register, 18-9
BEPDEF3 register, 18-9
BEPSIZ register, 18-9
BHE signal
description, 3-11
emulator support, 4-2, 4-3
bit sampling, UART, 13-16
bit stuffing, definition, Glossary-1
bit unstuffing, definition, Glossary-1
block diagram
Am186CC microcontroller, 1-5
Am186CC/CH/CU microcontrollers, 1-4
Am186CH HDLC microcontroller, 1-5
Am186CU USB microcontroller, 1-5
chip select, 5-2
DMA, 8-3
DRAM, 6-2
GCI, 17-1
HDLC, 15-2
HDLC receiver, 15-15
HDLC transmitter, 15-10
interrupt, 7-2
interrupt (partial), 7-15
maskable interrupt, 7-15
programmable I/O, 9-1
synchronous serial interface, 14-1
TSA, 16-3
typical system, 3-29
UART, 13-2
USB, 18-2
watchdog timer, 11-1
BOUNDS exception interrupt, 7-20
BRCVPK register, 18-9
break detection and generation, UART, 13-20
break, definition, Glossary-1
breakpoint interrupt, 7-19
BRI, definition, Glossary-1
Index-2
B
Am186™CC/CH/CU Microcontrollers User's Manual
Index
BSIZE8 signal
description, 3-11
emulator support, 4-3
buffer
adding, 8-32, 8-34
descriptor ring, creating, 8-31, 8-33
descriptor ring, definition, Glossary-1
queues, using, 8-20
replacing, 8-35
buffer queue, definition, Glossary-1
buffer, definition, Glossary-1
bulk transfer, definition, Glossary-1
bus
address bus description, 3-10, 3-13
bus status pins, 3-13
data. See data bus.
GCI. See GCI bus.
system. See system bus.
bus interface, signal list, 3-10
byte transfers, DMA, 8-15
byte write enables, 3-31
byte, definition, Glossary-1
C/I channel, GCI, 17-15
C/I0 arbitration, GCI, 17-18
CAS1–CAS0 signals
description, 3-19
emulator support, 4-3
CCIT, definition, Glossary-1
CDRAM register, 6-3
CEPBUFS register, 18-9
CEPCTL register, 18-9
CEPDAT register, 18-9
CEPDEF1 register, 18-9
CEPDEF2 register, 18-9
CEPDEF3 register, 18-9
CEPSIZ register, 18-9
chip select
block diagram, 5-2
comparison to other devices, 5-11
configuring address and data buses, 5-9
DRAM signal functions, 5-7
hardware considerations, 5-10
I/O space, 5-7
I/O, selecting, 5-5
initialization, 5-11
LCS signal, 5-5
MCS3–MCS0 signals, 5-5
memory space, 5-6
memory, selecting, 5-5
multiplexed signals, 5-3
C