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AMD AM186EM manual available for free PDF download: User Manual
AMD AM186EM User Manual (186 pages)
Brand:
AMD
| Category:
Microcontrollers
| Size: 1.46 MB
Table of Contents
Table of Contents
5
Design Philosophy
13
Intended Audience
13
Preface
13
Purpose of this Manual
13
User's Manual Overview
13
Amd Documentation
14
E86 Family
14
Introduction and Overview
13
Chapter 1 Features and Performance
15
Key Features and Benefits
15
Distinctive Characteristics
16
Application Considerations
19
Clock Generation
19
Figure 1-3 Basic Functional System Design
19
Memory Interface
20
Serial Communications Port
20
Third-Party Development Support Products
20
Chapter 2 Programming
21
Register Set
21
Processor Status Flags Register
22
Figure 2-1 Register Set
22
Figure 2-2 Processor Status Flags Register (F)
22
Memory Organization and Address Generation
23
Figure 2-3 Physical Address Generation
24
Figure 2-4 Memory and I/O Space
24
I/O Space
24
Instruction Set
24
Table 2-1 Instruction Set
25
Data Types
28
Segments
28
Figure 2-5 Supported Data Types
29
Addressing Modes
30
Chapter 3 System Overview
31
Bus Operation
46
Bus Interface Unit
49
Nonmultiplexed Address Bus
49
Byte Write Enables
49
Pseudo Static RAM (PSRAM) Support
49
Clock and Power Management Unit
50
Phase-Locked Loop (PLL)
50
Crystal-Driven Clock Source
50
Figure 3-5 Oscillator Configurations
51
External Source Clock
52
System Clocks
52
Power-Save Operation
52
Figure 3-6 Clock Organization
52
Chapter 4 Peripheral Control Block
53
Initialization and Processor Reset
60
Table 4-1 Table
61
Pin Descriptions
31
Pins that Are Used by Emulators
45
Overview
53
Peripheral Control Block Relocation Register
56
Reset Configuration Register (RESCON, Offset F6H)
57
Processor Release Level Register (PRL, Offset F4H)
58
Table 2-3 Table
58
Power-Save Control Register (PDCON, Offset F0H)
59
Chapter 5 Chip Select Unit
63
Overview
63
Chip Select Timing
64
Ready and Wait-State Programming
64
Chip Select Overlap
64
Chip Select Registers
65
Upper Memory Chip Select Register (UMCS, Offset A0H)
66
Figure 5-1 Upper Memory Chip Select Register
66
Table 5-2 UMCS Block Size Programming Values
66
Low Memory Chip Select Register (LMCS, Offset A2H)
68
Figure 5-2 Low Memory Chip Select Register
68
Table 5-3 LMCS Block Size Programming Values
68
Midrange Memory Chip Select Register (MMCS, Offset A6H)
70
Figure 5-3 Midrange Memory Chip Select Register
70
PCS and MCS Auxiliary Register (MPCS, Offset A8H)
72
Figure 5-4 PCS and MCS Auxiliary Register
72
Table 5-4 MCS Block Size Programming
72
Peripheral Chip Select Register (PACS, Offset A4H)
74
Figure 5-5 Peripheral Chip Select Register
74
Table 4-3 Table
75
Table 5-5 PCS Address Ranges
75
Table 5-6 PCS3-PCS0 Wait-State Encoding
75
Chapter 6 Refresh Control Unit
77
Overview
77
Memory Partition Register (MDRAM, Offset E0H)
77
Figure 6-1 Memory Partition Register
77
Clock Prescaler Register (CDRAM, Offset E2H)
78
Enable RCU Register (EDRAM, Offset E4H)
78
Figure 6-2 Clock Prescaler Register
78
Figure 6-3 Enable RCU Register
78
Chapter 7 Interrupt Control Unit
79
Overview
79
Definitions of Interrupt Terms
79
Interrupt Conditions and Sequence
82
Interrupt Priority
83
Software Exceptions, Traps, and NMI
84
Interrupt Acknowledge
85
Figure 7-1 External Interrupt Acknowledge Bus Cycles
85
Interrupt Controller Reset Conditions
86
Master Mode Operation
87
Fully Nested Mode
87
Figure 7-2 Fully Nested (Direct) Mode Interrupt Controller Connections
87
Cascade Mode
88
Figure 7-3 Cascade Mode Interrupt Controller Connections
88
Special Fully Nested Mode
89
Operation in a Polled Environment
89
End-Of-Interrupt Write to the EOI Register
89
Master Mode Interrupt Controller Registers
90
Table 7-2 Interrupt Controller Registers in Master Mode
90
Figure 7-4 INT0 and INT1 Control Registers
91
INT0 and INT1 Control Registers (I0CON, Offset 38H, I1CON, Offset 3Ah) (Master Mode)
91
Table 7-3 Priority Level
92
Figure 7-5 INT2 and INT3 Control Registers
93
INT2 and INT3 Control Registers (I2CON, Offset 3Ch, I3CON, Offset 3Eh) (Master Mode)
93
Figure 7-6 INT4 Control Register
94
INT4 Control Register (I4CON, Offset 40H) (Master Mode)
94
Figure 7-7 Timer/Dma Interrupt Control Registers
95
Timer and DMA Interrupt Control Registers (TCUCON, Offset 32H, DMA0CON, Offset 34H, DMA1CON, Offset 36H) (Master Mode)
95
Watchdog Timer Interrupt Control Register
96
Offset 42H) (Master Mode)
96
Serial Port Interrupt Control Register (SPICON, Offset 44H)
97
(Master Mode)
97
Interrupt Status Register (INTSTS, Offset 30H)
98
(Master Mode)
98
Interrupt Request Register (REQST, Offset 2Eh)
99
(Master Mode)
99
In-Service Register (INSERV, Offset 2Ch)
100
(Master Mode)
100
Priority Mask Register (PRIMSK, Offset 2Ah) (Master Mode)
101
Interrupt Mask Register (IMASK, Offset 28H) (Master Mode)
102
Poll Status Register (POLLST, Offset 26H) (Master Mode)
103
Poll Register (POLL, Offset 24H) (Master Mode)
104
End-Of-Interrupt Register (EOI, Offset 22H) (Master Mode)
105
Slave Mode Operation
106
Slave Mode Interrupt Nesting
106
Slave Mode Interrupt Controller Registers
106
Table 7-5 Interrupt Controller Registers in Slave Mode
106
Timer and DMA Interrupt Control Registers
107
3Ah, DMA0CON, Offset 34H, DMA1CON, Offset 36H)
107
(Slave Mode)
107
Interrupt Status Register (INTSTS, Offset 30H) (Slave Mode)
108
Interrupt Request Register (REQST, Offset 2Eh) (Slave Mode)
109
In-Service Register (INSERV, Offset 2Ch) (Slave Mode)
110
Priority Mask Register (PRIMSK, Offset 2Ah) (Slave Mode)
111
Table 7-6 Priority Level
111
Interrupt Mask Register (IMASK, Offset 28H) (Slave Mode)
112
Specific End-Of-Interrupt Register (EOI, Offset 22H)
113
(Slave Mode)
113
Interrupt Vector Register (INTVEC, Offset 20H) (Slave Mode)
114
Chapter 8 Timer Control Unit
115
Overview
115
Programmable Registers
115
Table 8-1 Timer Control Unit Register Summary
115
Timer Operating Frequency
116
Timer 0 and Timer 1 Mode and Control Registers (T0CON, Offset 56H, T1CON, Offset 5Eh)
117
Timer 2 Mode and Control Register (T2CON, Offset 66H)
119
Timer Count Registers (T0CNT, Offset 50H, T1CNT, Offset 58H, T2CNT, Offset 60H)
120
Timer Maxcount Compare Registers (T0CMPA, Offset 52H, T0CMPB, Offset 54H, T1CMPA, Offset 5Ah, T1CMPB, Offset 5Ch, T2CMPA, Offset 62H)
121
Chapter 9 Dma Controller
123
Overview
123
Dma Operation
123
Table 9-1 DMA Controller Register Summary
123
Programmable Dma Registers
124
DMA Control Registers
125
Table 9-2 Synchronization Type
126
DMA Transfer Count Registers
127
Offset D8H)
127
DMA Destination Address High Register (High Order Bits) (D0DSTH, Offset C6H, D1DSTH, Offset D6H)
128
DMA Destination Address Low Register (Low Order Bits) (D0DSTL, Offset C4H, D1DSTL, Offset D4H)
129
DMA Source Address High Register (High Order Bits) (D0SRCH, Offset C2H, D1SRCH, Offset D2H)
130
DMA Source Address Low Register (Low Order Bits) (D0SRCL, Offset C0H, D1SRCL, Offset D0H)
131
Dma Requests
132
Table 9-3 Maximum DMA Transfer Rates
132
Synchronization Timing
133
DMA Acknowledge
134
DMA Priority
134
DMA Programming
134
DMA Channels on Reset
135
Chapter 10 Asynchronous Serial Port
137
Overview
137
Programmable Registers
137
Table 10-1 Asynchronous Serial Port Register Summary
137
Table 10-2 Table
137
Serial Port Control Register (SPCT, Offset 80H)
138
Table 10-4 Table
139
Serial Port Status Register (SPSTS, Offset 82H)
140
Serial Port Transmit Data Register (SPTD, Offset 84H)
141
Serial Port Receive Data Register (SPRD, Offset 86H)
142
Serial Port Baud Rate Divisor Register (SPBAUD, Offset 88H)
143
Chapter 11 Synchronous Serial Interface
145
Overview
145
Four-Pin Interface
146
Programmable Registers
146
Synchronous Serial Status Register (SSS, Offset 10H)
147
Synchronous Serial Control Register (SSC, Offset 12H)
148
Synchronous Serial Transmit 1 Register (SSD1, Offset 14H) Synchronous Serial Transmit 0 Register (SSD0, Offset 16H)
149
Synchronous Serial Receive Register (SSR, Offset 18H)
150
Ssi Programming
151
Chapter 12 Programmable I/O Pins
153
Overview
153
Pio Mode Registers
155
PIO Mode 1 Register (PIOMODE1, Offset 76H)
155
PIO Mode 0 Register (PIOMODE0, Offset 70H)
155
Pio Direction Registers
156
PIO Direction 1 Register (PDIR1, Offset 78H)
156
PIO Direction 0 Register (PDIR0, Offset 72H)
156
Pio Data Registers
157
PIO Data Register 1 (PDATA1, Offset 7Ah)
157
PIO Data Register 0 (PDATA0, Offset 74H)
157
Open-Drain Outputs
157
Register Summary
159
Table A-1 Internal Register Summary
160
Table
161
Figure 4-1 Peripheral Control Block Relocation Register
162
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