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An Am186CC microcontroller access request can either be generated by software
(microprocessor access to C/I Channel 0) or by the HDLC controller itself (transmission of
an HDLC frame—signified internally by a signal, originating from the GCI TIC bus controller,
whose function is similar to an external RTS assertion). In the case of an access request,
the GCI TIC bus controller checks the BAC bit for the status "bus free" (BAC = 1). If the bus
is free, the GCI TIC bus controller starts transmitting its individual TIC bus address (the
source address indicated in Figure 17-9 by the TBA2–TBA0 bits). If an erroneous address
is detected, the procedure is terminated immediately. If the complete TIC bus address can
be transmitted without error, the D-channel and C/I Channel 0 are immediately occupied;
during the subsequent frames the bus is identified as occupied (BAC = 0) until the access
request is withdrawn. After a successful bus access, the HDLC controller is set into a lower
priority class, that is, a new bus access cannot be performed until the status "bus free"
(BAC = 1) is indicated in two successive frames.
If none of the D-channel protocol controllers connected to the GCI interface request access
to the D and C/I channels, the TIC Bus Address 7 is present. The device with this address
therefore has access, by default, to the D and C/I channels.
The following procedures gain access to the D-channel and C/I0 channel when TIC bus
support is enabled.
17.5.7.5.1
D-Channel Arbitration and Collision Detection (Hardware Control)
Hardware flow control for the GCI Bus Accessed (BAC) bit is added through RTS/CTS
handshaking, and follows a procedure very similar to the C/I0 arbitration scheme discussed
in "C/I0 Arbitration (Software Control)" on page 17-18.
1. The HDLC controller makes a D-channel send request to the GCI TIC bus controller by
asserting an internal RTS signal (this signal remains asserted until the entire HDLC
frame has been transmitted).
2. The GCI TIC bus controller checks if the BAC bit is set to 1. If not, access is not currently
allowed—transmission is postponed. Only when BAC = 1 does the GCI TIC bus controller
continue with this access procedure. Otherwise, it remains in this state.
3. When BAC = 1, the GCI TIC bus controller, in the same frame, transmits the TIC bus
address (TBA2–TBA0) on the open drain output. On the TIC bus, binary 0s overwrite
binary 1s. Therefore, low TIC bus addresses have higher priority. During TIC bus
reception, the S/G bit is monitored.
Note: S/G bit generation in the GCI TIC bus is sent downstream from an upstream
transceiver.
4. After transmitting a TIC bus address bit, the GCI TIC bus controller reads back the value
to check whether its own address bit has been overwritten by a controller with higher
priority. This procedure continues until all three address bits are sent and confirmed—
thus granting access to the GCI TIC bus. In the event a bit is overwritten by an external
controller with higher priority, the GCI TIC bus controller withdraws immediately from the
bus by setting all remaining TIC bus address bits to 1. (This assures that the lowest
address has priority. If the remaining bits are not immediately set to 1, addresses such
as 101 and 011 would have equal priority.) If a bit is overwritten and an address mismatch
occurs, the TIC bus controller returns to step 2.
5. If access is granted (i.e., no address mismatch occurred) and the S/G bit is 0 (i.e., the
S-interface is free for transmission), the GCI TIC bus controller asserts an internal CTS
signaling to the HDLC controller that it is now allowed to clock out data on its programmed
time slot starting in the following GCI frame. The BAC bit, during this HDLC transmission,
is set to 0 by the GCI TIC bus controller to block all remaining controllers.
General Circuit Interface (GCI)
Am186™CC/CH/CU Microcontrollers User's Manual
17-17
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