AMD Am186 CC User Manual page 255

transmitter status in the FABRST, CTSLST, TUFLO, TGOODF, and TSTOP bits of the
HxISTAT0 register.
Automatic CTS: When automatic CTS is enabled, the transmitter does not start
transmission until CTS is asserted. If the transmitter is transmitting (in-frame) and CTS
is deasserted, a lost CTS has occurred. A lost CTS halts transmission and generates
an abort and a maskable interrupt. If CTS is deasserted while the transmitter is in idle,
the transmitter does not respond. In multiplexed mode, the transmitter ignores CTS. If
CTS is deasserted in Transparent mode while transmitting, the transmitter begins
transmitting idles. When auto-enable CTS is disabled, the transmitter ignores the CTS
input. Auto-enable CTS must be disabled for Multidrop mode. To enable automatic CTS,
set the AUTOCTS bit of the HxTCON1 register to 1.
Multidrop Mode with Collision Detection: This mode requires the transmit data pin
to be physically tied, externally, to the CTS input pin. In addition, it requires the mark-
idle flag, disabled auto-enable CTS, and an open drain output. The HDLC channel delays
transmission until it sees a programmable number of consecutive 1s on the CTS input
pin. Specify the number of 1s to delay in the TDELAY field of the HxTCON1 register.
This feature provides some collision avoidance and a transmit priority based on the
number of 1s waited for before transmission. When transmission begins, the transmitter
samples the transmit data stream on the CTS input and internally compares it to what
is transmitted by the HDLC. Upon detecting a difference, the transmitter generates a
maskable interrupt (lost CTS), stops the data transmission, starts transmitting idle flags,
disables transmit, and flushes the transmit FIFO. To enable multidrop mode with collision
detection, set the MLTDRP bit of the HxTCON1 register to 1.
GCI D Channel Contention Resolution Request: The transmitter asserts a signal
CC
when it wants to send data. In the Am186CC microcontroller, the GCI controller asserts
a signal back indicating when access to the D channel is available. When the GCIDEN
bit of the HxTCON1 register is set to 1, the transmitter does not begin transmitting until
the GCI gives this indication. If the access signal is deasserted in the middle of
transmission, the transmitter immediately transmits an abort, starts transmitting idles,
generates a maskable interrupt, and indicates a lost CTS status. At the end of
transmission (after the closing flag), the transmitter briefly stops requesting access even
if additional frames are to be transmitted. See Chapter 17, "General Circuit Interface
(GCI)," for additional information.
Transmit Bit Order: The transmitter supports the option of transmitting data MSB first
instead of LSB. To specify MSB-first transmission, set the TMSBF bit in the HxTCON1
register to 1. This ability is typically used only in Transparent mode.
Transparent Mode: The transmitter supports a Transparent mode (set the TRANSM bit
of the HxCON register to 1) that transmits the data exactly as it appears in the FIFO.
Transparent mode does no bit stuffing, no framing with flags, and does not support CRC.
Transparent mode is useful for transmitting raw data streams such as audio data (for
use with a codec or DSP). To achieve byte alignment, synchronize the transmitter by
resetting the HDLC after configuring the TSA and HDLC. Raw DCE mode does not
support byte alignment. Additionally, byte alignment is not possible when the entire time-
multiplexed bus is allocated to a single TSA/HDLC channel. To enable Transparent mode,
set the TRANSM bit in the HxCON register to 1. Transparent mode is the opposite of
data transparency, where zero-bit insertion (bit stuffing) is used to ensure the receiver
does not recognize a flag, mark-idle, or abort in the data stream.
Figure 15-4 and Figure 15-5 show a typical transmit with auto-enable CTS enabled. CTS
goes active to start the transmission, which begins with a flag. After the flag, three bits of
data are transmitted before CTS is recognized as going inactive. This forces TXD High.
High-Level Data Link Control (HDLC)
Am186™CC/CH/CU Microcontrollers User's Manual 15-13