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High-Level Data Link Control (HDLC)
is independent of the threshold selected. The receiver can optionally generate a data-
ready interrupt as well.
Receive End-of-Frame: For programmed I/O, the REOF bit of the HxISTAT0 register
indicates when any status bytes (that is, an end-of-frame) are present in the FIFO. This
indication is independent of the threshold selected. The receiver can optionally generate
a status ready interrupt as well.
Receive-FIFO Overflow: If the receive FIFO overflows, it halts reception of the current
frame, disables the receiver, deasserts RTR, and generates a maskable interrupt. The
controller puts the overflow status into the receive FIFO when space is available. The
ROFLO bit of the HxISTAT1 register indicates when a receive-FIFO overflow occurs.
Bit Residue: If the number of bits in a frame is not an integer multiple of eight, the
receiver rejects the frame and reports the error status in the third status byte read from
the HxRD register. The last byte reported of the frame may or may not contain the
incomplete last byte of the frame.
Receiver Enable: When the receiver is disabled, the receiver continues to receive the
current frame. When the current frame ends (including the closing flag), or immediately
if not in-frame, the receiver deasserts the Ready-to-Receive (RTR) signal, and generates
a maskable interrupt. After the RTR signal is deasserted, the receiver does not receive
any data. When the receiver is re-enabled, it asserts the RTR signal. After reasserting
the RTR signal, it does not receive any data until it detects a flag and goes to the in-
frame state. When the receiver is disabled in Transparent mode, it immediately deasserts
the RTR signal and stops reception. When the receiver is enabled in Transparent mode,
it immediately asserts the RTR signal and starts reception. Disable the receiver by
clearing the HREN bit of the HxRCON0 register to 0.
Receive Reject: When receive reject is enabled, the receiver immediately stops
reception of data and reports an error status if the event occurred while in-frame. The
RTR signal is not affected. When receive reject is disabled, the receiver starts looking
for a flag. To enable receive reject, set the RREJECT bit of the HxRCON0 register to 1.
Receiver Stop: When the receiver is stopped, the receiver immediately stops reception
of data and deasserts RTR. The receiver also generates an error status if the event
occurred while in-frame. To stop the receiver, set the RSTOP bit of the HxRCON0 register
to 1.
Link Status: The status of the receiver is reported through the link status. The possible
states are: flag idle, mark idle, abort, and in-frame. For each state, the receiver can
generate a maskable interrupt when it enters the state. After receiving a flag, a
continuous input of 1s goes directly to the mark-idle state without transitioning to the
abort state. After exiting reset and a valid state is identified, the receiver always reports
the last valid state detected. Read the link status in the RTRS, ABORTS MARKIS,
FLAGS, and FRAMES bits of the HxSTATE register. Read the interrupts for these states
in the HxISTAT1 register.
Receive Bit Order: The receiver supports the option of receiving data MSB first instead
of LSB first. To specify MSB first reception, set the RMSBF bit of the HxRCON0 register
to 1. This ability is typically used only in Transparent mode.
Transparent Mode: The receiver supports a Transparent mode that moves the data into
the FIFO exactly as it is received with no bit stuffing, flag/abort detection, or CRC support.
To achieve byte alignment, synchronize the receiver through an HDLC reset after
configuring the Time Slot Assigner (TSA) and the HDLC. Raw DCE mode does not
support byte alignment. Additionally, alignment is not possible when the entire time-
Am186™CC/CH/CU Microcontrollers User's Manual
15-17
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