AMD Am186 CC User Manual page 312

Endpoint Control/Status (xEPCTL):
This register controls various aspects of the data endpoint. Because the data endpoint
is flexible in terms of the endpoint type, direction, and mode, besides other programmable
features, use of this register is discussed in the following specific application scenarios.
18.5.1.4.1 Endpoint A Configured as Bulk OUT, Non-DMA Mode
1. Program the Endpoint A registers:
– Set EP_TYPE = 10b (Bulk) and EP_DIR = 1 (OUT) in the AEPDEF1 register.
– Set MODE = 000b (Non-DMA) in the AEPDEF3 register.
– If interrupts are to be used, set the appropriate bits in the UIMASK1 or UIMASK2
register. If endpoint status bits are to generate interrupts, also set the appropriate
mask bits in the AEPDEF3 register.
– Perform any additional programming of the definition registers that is required for the
specific application.
2. Enable the data endpoint by setting the EP_EN bit in the AEPCTL register.
3. Assign initial control of the data FIFO to the USB endpoint hardware by clearing the
ACT_REQ bit in the IEPCTL register.
Data sent by the host is written to the data FIFO. At the end of a successful transfer,
hardware sets the ACT_REQ bit to transfer control to software. To enable this bit as an
interrupt source, set the A_EP_ACT bit in the UIMASK1 register.
4. When the ACT_REQ bit is set, read the endpoint FIFO (AEPDAT). Note that the number
of bytes written by the host can be obtained from the AEPSIZ register.
5. After reading the appropriate number of bytes from the FIFO, clear the ACT_REQ bit to
give control back to the USB endpoint hardware and allow it to reuse the FIFO for
subsequent data.
18.5.1.4.2 Endpoint A Configured as Bulk IN, Non-DMA Mode
1. Program the Endpoint A registers:
– Set EP_TYPE = 10b (Bulk) and EP_DIR = 0 (IN) in the AEPDEF1 register.
– Set MODE = 000b (Non-DMA) in the AEPDEF3 register.
– If interrupts are to be used, set the appropriate bits in the UIMASK1 or UIMASK2
register. If endpoint status bits are to generate interrupts, also set the appropriate
mask bits in the AEPDEF3 register.
– Perform any additional programming of the definition registers that is required for the
specific application.
2. Enable the data endpoint by setting the EP_EN bit in the AEPCTL register.
3. For an IN endpoint, initial control of the data FIFO is assigned to the device. Device
software can therefore write to the endpoint FIFO (AEPDAT) when it is ready.
4. After it is finished writing to AEPDAT, software should clear the ACT_REQ bit in the
IEPCTL register to give control back to the USB endpoint hardware and allow it to transmit
the written data.
Hardware sets the ACT_REQ bit after the endpoint has successfully sent a data packet
to the host and the packet has been acknowledged. To enable the ACT_REQ bit as an
interrupt source, set the A_EP_ACT bit in the UIMASK1 register.
18-14
Universal Serial Bus (USB)
Am186™CC/CH/CU Microcontrollers User's Manual