Table of Contents
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types, 2-8, 2-9
UART
data overflow, 13-8
description, 13-8
receiving, 13-7, 13-10
USB
control endpoint, 18-29
interrupt endpoint, 18-30
transmission types, 18-16
data bus
configuring chip select, 5-9
overview, 3-30
data endpoint
defining, 18-32
definition, Glossary-2
DCE (data communications equipment)
definition, Glossary-2
signal descriptions, 3-23
DCE_CTS_A signal, 3-24
DCE_CTS_B signal, 3-24
DCE_CTS_C signal, 3-24
DCE_CTS_D signal, 3-25
DCE_RCLK_A signal, 3-23
DCE_RCLK_B signal, 3-24
DCE_RCLK_C signal, 3-24
DCE_RCLK_D signal, 3-25
DCE_RTR_A signal, 3-24
DCE_RTR_B signal, 3-24
DCE_RTR_C signal, 3-25
DCE_RTR_D signal, 3-25
DCE_RXD_A signal, 3-23
DCE_RXD_B signal, 3-24
DCE_RXD_C signal, 3-24
DCE_RXD_D signal, 3-25
DCE_TCLK_A signal, 3-23
DCE_TCLK_B signal, 3-24
DCE_TCLK_C signal, 3-24
DCE_TCLK_D signal, 3-25
DCE_TXD_A signal, 3-23
DCE_TXD_B signal, 3-24
DCE_TXD_C signal, 3-24
DCE_TXD_D signal, 3-25
D-channel, GCI, 17-17
deactivation, GCI, 17-10
debug support signals, 3-17
decrementing DMA address, 8-15
default address, definition, Glossary-2
DEN signal, 3-11
DEPBUFS register, 18-9
DEPCTL register, 18-9
DEPDAT register, 18-9
Index-4
Index
Am186™CC/CH/CU Microcontrollers User's Manual
DEPDEF1 register, 18-9
DEPDEF2 register, 18-9
DEPDEF3 register, 18-9
DEPSIZ register, 18-9
descriptor format, 8-38
descriptor ring
creating, 8-31, 8-33
definition, Glossary-2
transmit, 8-30, 8-31
destination
address, 8-13
synchronization, 8-10
destination-synchronized transfer
definition, Glossary-2
description, 8-18
detectable baud ranges, 13-17
device address, definition, Glossary-2
device, definition, Glossary-2
differences, controller, xxiii
disconnect, USB, 18-3
divide error exception interrupt, 7-19
DMA
See also SmartDMA channel.
acknowledge, 8-10
adding data buffers, 8-32, 8-34
availability, 18-19
block diagram, 8-3
byte or word transfers, 8-15
channel use, 8-8, 8-9
circular buffers, 8-23
comparison to other devices, 8-43
create descriptor ring, 8-31, 8-33
deasserting DRQ, 8-19
decrementing address, 8-15
definition, Glossary-2
destination synchronization, 8-10, 8-18
enabling
peripheral device, 8-35
receive channel, 8-33, 8-35
transmit channel, 8-31, 8-33
FIFO interaction, 18-20
general-purpose
channels, 8-11
cycle, 8-12
data transfers, 8-11
interrupts, 8-13
operations, 8-14
request source, 8-17
source and destination addresses, 8-13
synchronization, 8-17
terminal count, 8-14
usage, 8-12
generating interrupts, 8-15
hardware flow control, 8-24
incrementing address, 8-15
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