AMD Am186 CC User Manual page 63

Table 3-7 Signal Descriptions (Continued)
Multiplexed
1
Signal Name
Signal(s)
HOLD
RD
S2
S1
S0 {USBXCVR}
S6
System Overview
Type Description
Bus-Hold Request indicates to the microcontroller that an
external bus master needs control of the local bus.
The microcontroller HOLD latency time—the time between
HOLD request and HOLD acknowledge—is a function of the
activity occurring in the processor when the HOLD request is
received. A HOLD request is second only to DRAM refresh
requests in priority of activity requests received by the processor.
This implies that if a HOLD request is received just as a DMA
transfer begins, the HOLD latency can be as great as four bus
cycles. This occurs if a DMA word transfer operation is taking
— STI
place from an odd address to an odd address. This is a total of
16 clock cycles or more if wait states are required. In addition,
if locked transfers are performed, the HOLD latency time is
increased by the length of the locked transfer. HOLD latency is
also potentially increased by DRAM refreshes.
The board designer is responsible for properly terminating the
HOLD input.
For more information, see the HLDA pin description above.
Read Strobe indicates to the system that the microcontroller is
performing a memory or I/O read cycle. RD is guaranteed not to
— O be asserted before the address and data bus is three-stated
during the address-to-data transition. RD is three-stated with a
pullup during bus-hold or reset conditions.
Bus Cycle Status 2–0 indicate to the system the type of bus
cycle in progress. S2 can be used as a logical memory or I/O
indicator, and S1 can be used as a data transmit or receive
indicator. S2–S0 are three-stated during bus hold and three-
stated with a pullup during reset. The S2–S0 pins are encoded
as follows:
—
— O
Bus Cycle Status Bit 6: This signal is asserted during t
indicate a DMA-initiated bus cycle or a refresh cycle. S6 is three-
— O
stated during bus hold and three-stated with a pulldown during
reset.
Am186™CC/CH/CU Microcontrollers User's Manual
Bus Status Pins
S2 S1 S0 Bus Cycle
0 0 0 Reserved
0 0 1 Read data from I/O
0 1 0 Write data to I/O
0 1 1 Halt
1 0 0 Instruction fetch
1 0 1 Read data from memory
1 1 0 Write data to memory
1 1 1 None (passive)
–t to
1 4
3-13