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High-Level Data Link Control (HDLC)
The HDLC transmitters have the following features:
Transmit FIFO: The transmit FIFO consists of a 16-byte FIFO buffer, end-of-frame logic,
and DMA-request logic. When using programmed I/O to fill the transmit FIFO, a bit must
be set after the last byte in a frame is written to the FIFO. The SmartDMA interface uses
the terminal count signal from the DMA controller. For more information, see Chapter 8,
"DMA Controller." Read the transmit FIFO with the HxTD register.
Transmit-FIFO Interface: When the transmit FIFO requests data, it either generates
an internal DMA request or sets the TDATA1 bit in the HxISTAT0 register indicating
transmit space is available. This status bit being set can generate a maskable interrupt.
Transmit-FIFO Threshold: The transmit FIFO has three options for the level at which
it requests data, specified in the TTHRSH field of the HxTCON0 register:
– When there is space available in the transmit FIFO (TTHRSH = 00)
– When there are 9 bytes of FIFO space available (TTHRSH = 01)
– When there are 16 bytes of FIFO space available (TTHRSH = 10)
Reaching the transmit threshold also generates a maskable interrupt (indicated in the
TTHRES bit of the HxISTAT0 register).
Transmit-Space Available: For programmed I/O, the TDATA1 bit in the HxISTAT0
register indicates when there is space available in the transmit FIFO. This indication is
independent of the threshold selected. The space available status can also generate a
maskable interrupt.
Transmit-FIFO Underflow: When the transmit FIFO underflows, it generates a
maskable interrupt, enters the abort state, and reports a TUFLO error status.
Transmit-Clock Polarity: The transmit clock polarity is specified in the TXCINV bit of
the HxTCON1 register, independent of the receive clock polarity. This feature is
recommended for use only in DCE mode.
Immediate-Transmit Start: When immediate transmit start is enabled, the transmitter
begins transmitting as soon as data is available in the transmit FIFO. When immediate
transmit start is disabled, the transmitter does not start transmitting until the FIFO is half
full or the complete frame is in the FIFO, whichever comes first. To enable immediate
transmit start, set the IMSTART bit in the HxTCON0 register to 1.
Flag- or Mark-Idle Generation: The HDLC transmitter can transmit either flag- or mark-
idles when the transmitter is enabled and is not actively sending a data frame (including
the opening and closing flags) or an abort sequence. Specify a flag idle by setting the
FLAGIDL bit in the HxTCON1 register to 1; specify a mark idle by clearing the FLAGIDL
bit to 0. A flag is 7Eh (the sequence of one 0, six 1s, and one 0); a mark idle sequence
is fifteen 1s; an abort sequence is one 0 followed by from seven to 14 consecutive 1s.
To properly support multidrop configurations with collision detection, the HDLC
transmitter should be configured to generate mark-idles. When transmitting flag- or mark-
idles, the transmitter is in the idle condition.
Flag Generation with Back-to-Back Frames: The minimum number of flags between
frames transmitted is two. At least one closing flag is always generated at the end of a
frame, and at least one opening frame is generated at the beginning of a frame (except
in Transparent mode). Back-to-back flags are sent without sharing 0s (i.e.,
0111111001111110, not 011111101111110).
Am186™CC/CH/CU Microcontrollers User's Manual
15-11
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