Gp Bus; Gp-Dma Controller; Programmable Interval Timer; General-Purpose Timers - AMD Elan SC520 User Manual

CPU reset, see the Am486
(order #17965).
Note: The CFG3–CFG0 and RSTLD7–RSTLD0 pins are latched only as a result of the
assertion of the PWRGOOD signal, and not as a result of the SYS_RST bit, AMDebug
system reset event, or watchdog timer event.
If the ICE_ON_RST bit in the Reset Configuration (RESCFG) register is set to a 1, the
AMDebug utility enters into AMDebug mode after system reset.
The states of the ÉlanSC520 microcontroller cores after system reset are shown in
Table 6-4. See the "Initialization" section at the end of each chapter for more detailed
information.
Table 6-4 States of Cores after System Reset
Core
Am5 86 CPU
x
System arbiter
PCI host bridge master controller
PCI host bridge target controller
SDRAM controller
Write buffer and read buffer
ROM controller
GP bus controller

GP-DMA controller

Programmable interrupt controller
(PIC)

Software timer

General-purpose (GP) timers
Programmable interval timer (PIT)
Watchdog timer (WDT)
Real-time clock (RTC)
UARTs
Synchronous serial interface (SSI)
Programmable input/output (PIO)
pins
JTAG test access port (TAP)
AMDebug mode
Reset Generation
®
DX/DX2 Microprocessor Hardware Reference Manual , 1994
State
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Enabled
Disabled
Disabled
Enabled
Enabled
Enabled
Élan™SC520 Microcontroller User's Manual
Comment
CPU clock frequency is set to 100 MHz. Internal
registers and internal cache are reset.
Default is nonconcurrent arbitration mode. All bus
masters are disabled except the CPU as PCI and
internal Am5 86 CPU bus master.
x
No banks are enabled.
BOOTCS (only) is enabled at system reset
External GP bus is disabled until PAR registers are
initialized.
All channels are masked off.
Interrupts are masked at the CPU. NMIs are
disabled.
All GP timer registers are reset to 0. Each timer must
be programmed before it can be used.
Each PIT channel must be programmed before it
can be used.
Inactive until an SSI command is written.
All PIO pins default to inputs and to their PIO
function.
JTAG_TRST should be asserted active Low to
ensure normal operation.
If the ICE_ON_RST bit in the Reset Configuration
(RESCFG) register is set.
6-5