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Intel BX80619I73960X Datasheet

Core i7 extreme edition processor family for the lga-2011 socket
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®
Intel
Core™ i7 Processor Family for
the LGA-2011 Socket
Datasheet, Volume 1
Supporting Desktop Intel
Processor for the LGA-2011 Socket
Supporting Desktop Intel
for the LGA-2011 Socket
This is volume 1 of 2.
November 2012
®
Core™ i7-3960X and i7-3970X Extreme Edition
®
Core™ i7-39xxK and i7-38xx Processor Series
Reference Number:
326196-002

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Summary of Contents for Intel BX80619I73960X

  • Page 1 ® Intel Core™ i7 Processor Family for the LGA-2011 Socket Datasheet, Volume 1 ® Supporting Desktop Intel Core™ i7-3960X and i7-3970X Extreme Edition Processor for the LGA-2011 Socket ® Supporting Desktop Intel Core™ i7-39xxK and i7-38xx Processor Series for the LGA-2011 Socket This is volume 1 of 2.
  • Page 2 Do not finalize a design with this information. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Hyper-Threading Technology requires a computer system with a processor supporting HT Technology and an HT Technology enabled chipset, BIOS and operating system.

  • Page 3: Table Of Contents

    VT-d) Processor Feature Additions ....23 ® 3.1.4 Intel Virtualization Technology Processor Extensions ......... 23 Security Technologies ..................24 ® ® 3.2.1 Intel AES New Instructions (Intel AES-NI) ..........24 3.2.2 Execute Disable Bit................. 24 ® ® Intel Hyper-Threading Technology (Intel HT Technology)........24 ®...
  • Page 4 4.1.4 DMI2 / PCI Express* Link States...............29 4.1.5 G, S, and C State Combinations..............30 Processor Core / Package Power Management ............30 ® ® 4.2.1 Enhanced Intel SpeedStep Technology ..........30 4.2.2 Low-Power Idle States................31 4.2.3 Requesting Low-Power Idle States ............32 4.2.4 Core C-states ..................32...
  • Page 5 7.1.8.1 Power and Ground Lands ............51 7.1.8.2 Decoupling Guidelines ............... 52 7.1.8.3 Voltage Identification (VID)............52 7.1.9 Reserved or Unused Signals..............56 Signal Group Summary ..................56 Power-On Configuration (POC) Options..............59 Absolute Maximum and Minimum Ratings ............. 60 7.4.1 Storage Conditions Specifications .............
  • Page 6 DMI2 to Port 0 Signals..................44 PECI Signals .....................44 System Reference Clock (BCLK{0/1}) Signals............44 6-10 JTAG and TAP Signals..................45 6-11 SVID Signals .....................45 6-12 Processor Asynchronous Sideband Signals.............46 6-13 Miscellaneous Signals ..................47 6-14 Power and Ground Signals ..................48 Power and Ground Lands ..................51 SVID Address Usage ..................54 Voltage Identification Definition ................55 Signal Description Buffer Types ................56...

  • Page 7: Revision History

    Revision History Revision Description Revision Date Number • Initial Release November 2011 • Updated to clarify references to PCI Express* November 2012 ® • Added Intel Core™ i7-3970X Processor Extreme Edition § Datasheet, Volume 1...
  • Page 8 Datasheet, Volume 1...

  • Page 9: Introduction

    I/O (IIO) (such as PCI Express* and DMI2) on a single silicon die. This single die solution is known as a monolithic processor. ® This document is Volume 1 of the datasheet for the Intel Core™ i7 processor family for the LGA-2011 socket. The complete datasheet consists of two volumes. This...

  • Page 10: Processor Feature Details

    Processor Feature Details • Up to 6 Execution Cores ® • Each core supports two threads (Intel Hyper-Threading Technology) for up to 12 threads • A 32-KB instruction and 32-KB data first-level cache (L1) for each core •...

  • Page 11: Interfaces

    Introduction Interfaces 1.2.1 System Memory Support • The processor supports 4 DDR3 channels with 1 unbuffered DIMM per channel • Unbuffered DDR3 DIMMs supported • Data burst length of eight cycles for all memory organization modes • Memory DDR3 data transfer rates of 1066, 1333, and 1600 MT/s •...

  • Page 12: Pci Express* Lane Partitioning And Direct Media Interface Gen 2 (Dmi2)

    • Supports receiving and decoding 64 bits of address from PCI Express* — Memory transactions received from PCI Express* that go above the top of physical address space (when Intel VT-d is enabled, the check would be against the translated HPA (Host Physical Address) address) are reported as errors by the processor.

  • Page 13: Direct Media Interface Gen 2 (Dmi2)

    • Transparent to software • Processor and peer-to-peer writes and reads with 64-bit address support • APIC and Message Signaled Interrupt (MSI) support. Will send Intel-defined “End of Interrupt” broadcast message when initiated by the processor. • System Management Interrupt (SMI), SCI, and SERR error indication •...

  • Page 14: Thermal Management Support

    Execute Disable Bit can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities ® and can thus help improve the overall security of the system. See the Intel 64 and IA-32 Architectures Software Developer's Manuals for more detailed information.
  • Page 15 ® Intel VT-d device virtualization. Intel VT-d also brings robust security by providing protection from errant DMAs by using DMA remapping, a key feature of Intel VT-d. Integrated Heat A component of the processor package used to enhance the thermal performance of the Spreader (IHS) package.

  • Page 16: Related Documents

    Core™ i7 Processor Family for the LGA-2011 Socket Datasheet, Volume 2 ® 326198 Intel Core™ i7 Processor Family for the LGA-2011 Socket Specification Update ® Desktop Intel Core™ i7 Processor Family for the LGA-2011 Socket Thermal 326199 Mechanical Specifications and Design Guide ® 326200...

  • Page 17: Interfaces

    Interfaces Interfaces This chapter describes the functional behaviors supported by the processor. System Memory Interface 2.1.1 System Memory Technology Support The Integrated Memory Controller (IMC) supports DDR3 protocols with four independent 64-bit memory channels and supports 1 unbuffered DIMM per channel. 2.1.2 System Memory Timing Support The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and...

  • Page 18: Transaction Layer

    Interfaces Figure 2-1. PCI Express* Layering Diagram Transaction Transaction Transaction Transaction Data Link Data Link Data Link Data Link Physical Physical Physical Physical Logical Sub-Block Logical Sub-Block Logical Sub-Block Logical Sub-Block Electrical Sub-Block Electrical Sub-Block Electrical Sub-Block Electrical Sub-Block PCI Express uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component.

  • Page 19: Physical Layer

    Interfaces The transmission side of the Data Link Layer accepts TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP sequence number, and submits them to Physical Layer for transmission across the Link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing.

  • Page 20: Dmi2 Link Down

    In this way, it is highly flexible even though underlying logic is simple. The interface design was optimized for interfacing to Intel processor and chipset components in both single processor and multiple processor environments. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components.

  • Page 21: Technologies

    • Enhanced: Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors. • More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient.

  • Page 22: Vt-X) Features

    Directed I/O (Intel VT-d) Objectives The key Intel VT-d objectives are abstraction and robustness. Hardware abstraction has two key benefits. First is partitioning hardware into configurable isolated environments called domains to which a subset of host physical memory is allocated. Second is greater flexibility in modifying hardware capability without direct operating system interference.

  • Page 23: Virtualization Technology

    LGA-2011 socket Extensions features: • Large Intel VT-d Pages — Adds 2 MB and 1 GB page sizes to Intel VT-d implementations — Matches current support for Extended Page Tables (EPT) — Ability to share CPU's EPT page-table (with super-pages) with Intel VT-d —...

  • Page 24: Security Technologies

    3.2.2 Execute Disable Bit Intel's Execute Disable Bit functionality can help prevent certain classes of malicious buffer overflow attacks when combined with a supporting operating system: • Allows the processor to classify areas in memory by where application code can execute and where it cannot.

  • Page 25: Hyper-Threading Technology

    TDP limit. Note: Intel Turbo Boost Technology is only active if the operating system is requesting the P0 state. For more information on P-states and C-states, refer to Chapter 4, "Power Management".

  • Page 26: Intel Advanced Vector Extensions (Intel Avx)

    3D modeling and analysis, scientific simulation, and financial analysts. Intel AVX is a comprehensive ISA extension of the Intel 64 Architecture. The main elements of Intel AVX are: • Support for wider vector data (up to 256-bit) for floating-point computation •...

  • Page 27: Power Management

    Power Management Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Power Interface (ACPI) States • System States • Processor Core/Package States • Integrated Memory Controller (IMC) and System Memory States • Direct Media Interface Gen 2 (DMI2)/PCI Express* Link States Advanced Configuration and Power Interface (ACPI) States Supported The ACPI states supported by the processor are described in this section.

  • Page 28: Package C-State Support

    Power Management Table 4-3 lists the processor core C-states support. Table 4-2. Package C-State Support Core Retention and Package C-State Limiting Factors Fully Notes States PLL-Off Flushed PC0 – Active • PCIe/PCH and Remote Socket Snoops • PCIe/PCH and Remote Socket VccMin Accesses PC2 –...

  • Page 29: Integrated Memory Controller States

    Power Management 4.1.3 Integrated Memory Controller States Table 4-4. System Memory Power States State Description Power Up/Normal Operation CKE asserted. Active Mode, highest power consumption. Opportunistic, per rank control after idle time: • Active Power Down (APD) (default mode) — CKE de-asserted. Power savings in this mode, relative to active idle state is about 55% of the memory power.

  • Page 30: G, S, And C State Combinations

    Enhanced Intel SpeedStep Technology ® The following are the key features of Enhanced Intel SpeedStep Technology: • Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on temperature, leakage, power delivery loadline, and dynamic capacitance.

  • Page 31: Low-Power Idle States

    Power Management 4.2.2 Low-Power Idle States When the processor is idle, low-power idle states (C-states) are used to save power. More power savings actions are taken for numerically higher C-states. However, higher C-states have longer exit and entry latencies. Resolution of C-states occur at the thread, processor core, and processor package level.

  • Page 32: Requesting Low-Power Idle States

    Power Management 4.2.3 Requesting Low-Power Idle States If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1 state or higher. The primary software interfaces for requesting low power idle states are through the MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).

  • Page 33: Core C0 State

    MWAIT(C1/C1E) instruction. A System Management Interrupt (SMI) handler returns execution to either Normal ® state or the C1/C1E state. See the Intel 64 and IA-32 Architecture Software Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information. While a core is in C1/C1E state, it processes bus snoops and snoops from other threads.

  • Page 34: Package C-States

    The package C-states fall into two categories – uncoordinated and coordinated. C0/C1/ C1E are uncoordinated, while C2/C3/C6 are coordinated. ® Starting with the 2nd Generation Intel Core™ Processor Family Desktop, package C- states are based on exit latency requirements which are accumulated from the PCIe* devices, PCH, and software sources.

  • Page 35: Package C0

    Power Management Table 4-8. Coordination of Core Power States at the Package Level Core 1 Package C-State Core 0 Notes: 1. If enabled, the package C-state will be C1E if all actives cores have resolved a core C1 state or higher. Figure 4-3.

  • Page 36: Package C2 State

    Power Management The package enters the C1E state when: • All cores have directly requested C1E using MWAIT(C1) with a C1E sub-state hint • All cores are in a power state lower that C1/C1E but the package low power state is limited to C1/C1E using the PMG_CST_CONFIG_CONTROL MSR •...

  • Page 37: Package C-State Power Specifications

    Power Management 4.2.6 Package C-State Power Specifications Table 4-9 lists the processor package C-state power specifications for various processor SKUs. The C-state power specification is based on post-silicon validation results. The processor case temperature is assumed at 50 °C for all C-states. Table 4-9.

  • Page 38: Self Refresh

    Power Management 4.3.2 Self Refresh The Uncore Power Manager (PCU) may request the memory controller to place the DRAMs in self refresh state. Self refresh per channel is supported. The BIOS can put the channel in self refresh if software remaps memory to use a subset of all channels. Also processor channels can enter self refresh autonomously without PCU instruction when the package is in a package C0 state.

  • Page 39: Thermal Management Specifications

    Thermal Management Specifications Thermal Management Specifications For thermal specifications and design guidelines, refer to the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, “Related Documents”). § Datasheet, Volume 1...
  • Page 40 Thermal Management Specifications Datasheet, Volume 1...

  • Page 41: Signal Descriptions

    Signal Descriptions Signal Descriptions This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. System Memory Interface Table 6-1. Memory Channel DDR0, DDR1, DDR2, DDR3 Signal Name Description Bank Address. Defines the bank which is the destination for the DDR{0/1/2/3}_BA[2:0] current Activate, Read, Write, or Precharge command.

  • Page 42: Pci Express* Based Interface Signals

    Signal Descriptions Table 6-2. Memory Channel Miscellaneous Signal Name Description System memory reset: Reset signal from processor to DRAM devices on the DDR_RESET_C01_N DIMMs. DDR_RESET_C01_N is used for memory channels 0 and 1 while DDR_RESET_C23_N DDR_RESET_C23_N is used for memory channels 2 and 3. SMBus clock for the dedicated interface to the serial presence detect (SPD) DDR_SCL_C01 and thermal sensors (TSoD) on the DIMMs.

  • Page 43: Pci Express* Port 2 Signals

    Signal Descriptions Table 6-4. PCI Express* Port 2 Signals Signal Name Description PE2A_RX_DN[3:0] PCIe Receive Data Input PE2A_RX_DP[3:0] PE2B_RX_DN[7:4] PCIe Receive Data Input PE2B_RX_DP[7:4] PE2C_RX_DN[11:8] PCIe Receive Data Input PE2C_RX_DP[11:8] PE2D_RX_DN[15:12] PCIe Receive Data Input PE2D_RX_DP[15:12] PE2A_TX_DN[3:0] PCIe Transmit Data Output PE2A_TX_DP[3:0] PE2B_TX_DN[7:4] PCIe Transmit Data Output...

  • Page 44: Dmi2 / Pci Express* Port 0 Signals

    Signal Descriptions Table 6-6. PCI Express* Miscellaneous Signals Signal Name Description This input is used to control PCI Express* bias currents. A 50 ohm 1% tolerance resistor must be connected from this land to V by the platform. PE_RBIAS PE_RBIAS is required to be connected as if the link is being used even when PCIe* is not used.

  • Page 45: Jtag And Tap Signals

    Signal Descriptions JTAG and TAP Signals Table 6-10. JTAG and TAP Signals Signal Name Description Breakpoint and Performance Monitor Signals: I/O signals from the processor BPM_N[7:0] that indicate the status of breakpoints and programmable counters used for monitoring processor performance. These are 100 MHz signals. External Alignment of Reset, used to bring the processor up into a deterministic EAR_N state.

  • Page 46: Processor Asynchronous Sideband And Miscellaneous Signals

    Signal Descriptions Processor Asynchronous Sideband and Miscellaneous Signals Table 6-12. Processor Asynchronous Sideband Signals (Sheet 1 of 2) Signal Name Description Input which allows the platform to enable or disable built-in self test (BIST) on the BIST_ENABLE processor. This signal is pulled up on the die; refer to Table 7-6 for details.
  • Page 47 This output can be used by the platform to determine if the installed ® processor is a Intel Core™ i7 processor family for the LGA-2011 socket or a PROC_SEL_N future processor planned for the platforms. There is no connection to the processor silicon for this signal.

  • Page 48: Processor Power And Ground Supplies

    Signal Descriptions Processor Power and Ground Supplies Table 6-14. Power and Ground Signals Signal Name Description Variable power supply for the processor cores, lowest level caches (LLC), ring interface, and home agent. It is provided by a VR12 compliant regulator. The output voltage of this supply is selected by the processor using the serial voltage ID (SVID) bus.

  • Page 49: Electrical Specifications

    7.1.4 Platform Environmental Control Interface (PECI) PECI is an Intel proprietary interface that provides a communication channel between Intel processors and chipset components to external system management logic and thermal monitoring devices. The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

  • Page 50: Input Device Hysteresis

    Electrical Specifications The PECI interface operates at a nominal voltage set by V . The set of DC electrical specifications shown in Table 7-13 is used with devices normally operating from a V interface supply. 7.1.4.1 Input Device Hysteresis The PECI client and host input buffers must use a Schmitt-triggered input design for improved noise immunity.

  • Page 51: Jtag And Test Access Port (Tap) Signals

    Due to the voltage levels supported by other components in the JTAG and Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage.

  • Page 52: Decoupling Guidelines

    Electrical Specifications 7.1.8.2 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate.
  • Page 53 The SetVID-slow command is preemptive, the VR interrupts its current processes and moves to the new VID. This is the instruction used for normal P-state voltage change. This command is used in the processor for the Intel Enhanced SpeedStep Technology transitions.

  • Page 54: Vr Power-State Transitions

    Electrical Specifications If a power state is not supported by the controller, the slave should acknowledge with command rejected (11b) If the VR is in a low power state and receives a SetVID command moving the VID up, then the VR exits the low power state to normal mode (PS0) to move the voltage up as fast as possible.

  • Page 55: Voltage Identification Definition

    Electrical Specifications Table 7-3. Voltage Identification Definition Vcc & Vsa Vcc & Vsa Vcc & Vsa Vcc & Vsa 0.00000 0.67000 0.84500 1.02000 1.19500 1.37000 0.50000 0.67500 0.85000 1.02500 1.20000 1.37500 0.50500 0.68000 0.85500 1.03000 1.20500 1.38000 0.51000 0.68500 0.86000 1.03500 1.21000 1.38500...

  • Page 56: Reserved Or Unused Signals

    Electrical Specifications 7.1.9 Reserved or Unused Signals All Reserved (RSVD) signals must not be connected. Connection of these signals to V , or to any other signal (including each other) can result in CCD, CCPLL component malfunction or incompatibility with future processors. See Chapter 8, "Processor Land Listing,"...

  • Page 57: Signal Groups

    Electrical Specifications Table 7-5. Signal Groups (Sheet 1 of 3) Differential/Single Buffer Type Signals Ended DDR3 Reference Clocks Differential SSTL Output DDR{0/1/2/3}_CLK_D[N/P][3:0] DDR3 Command Signals DDR{0/1/2/3}_BA[2:0] DDR{0/1/2/3}_CAS_N DDR{0/1/2/3}_MA[15:00] SSTL Output DDR{0/1/2/3}_MA_PAR Single ended DDR{0/1/2/3}_RAS_N DDR{0/1/2/3}_WE_N CMOS1.5v Output DDR_RESET_C{01/23}_N DDR3 Control Signals DDR{0/1/2/3}_CS_N[1:0] DDR{0/1/2/3}_CS_N[5:4] CMOS1.5v Output...
  • Page 58 Electrical Specifications Table 7-5. Signal Groups (Sheet 2 of 3) Differential/Single Buffer Type Signals Ended PCI Express* Miscellaneous Signals Analog Input PE_RBIAS_SENSE Single ended PE_RBIAS Reference Input/Output PE_VREF_CAP DMI2/PCI Express* Signals DMI2 Input DMI_RX_D[N/P][3:0] Differential DMI2 Output DMI_TX_D[N/P][3:0] Platform Environmental Control Interface (PECI) Single ended PECI PECI...

  • Page 59: Power-On Configuration (Poc) Options

    Electrical Specifications Table 7-5. Signal Groups (Sheet 3 of 3) Differential/Single Buffer Type Signals Ended Power/Other Signals VCC, VTTA, VTTD, VCCD_01, VCCD_23,VCCPLL, VSA Power / Ground and VSS VCC_SENSE VSS_VCC_SENSE VSS_VTTD_SENSE Sense Points VTTD_SENSE VSA_SENSE VSS_VSA_SENSE Notes: Refer to Chapter 6, "Signal Descriptions," for signal description details.

  • Page 60: Absolute Maximum And Minimum Ratings

    Electrical Specifications Absolute Maximum and Minimum Ratings Table 7-8 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits (but within the absolute maximum and minimum ratings) the device may be functional, but with its lifetime degraded depending on...

  • Page 61: Dc Specifications

    Electrical Specifications DC Specifications DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting the thermal specifications as specified in the processor Thermal Mechanical Specification and Design Guide (see Section 1.7, “Related Documents”), clock frequency, and input voltages.

  • Page 62: Current (Icc_Max And Icc_Tdc) Specification

    Electrical Specifications The processor should not be subjected to any static V level that exceeds the V associated TTA, TT_MAX with any particular current. Failure to adhere to this specification can shorten processor lifetime. 10. Baseboard bandwidth is limited to 20 MHz. 11.

  • Page 63: Die Voltage Validation

    Electrical Specifications 7.5.2 Die Voltage Validation Core voltage (V ) overshoot events at the processor must meet the specifications in Table 7-11 when measured across the VCC_SENSE and VSS_VCC_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot should be taken with a 100 MHz bandwidth limited oscilloscope.

  • Page 64: Signal Dc Specifications

    Electrical Specifications 7.5.3 Signal DC Specifications DC specifications are defined at the processor pads, unless otherwise noted. DC specifications are only valid while meeting specifications for case temperature (T CASE specified in the processor Thermal Mechanical Specification and Design Guide; see Section 1.7, “Related Documents”), clock frequency, and input voltages.

  • Page 65: Peci Dc Specifications

    Electrical Specifications This is the pull-down driver resistance. Reset drive does not have a termination. is the termination on the DIMM and not controlled by the processor. Refer to the applicable DIMM VTT_TERM datasheet. The minimum and maximum values for these signals are programmable by BIOS to one of the pairs. COMP resistance must be provided on the system board with 1% resistors.

  • Page 66: System Reference Clock (Bclk{0/1}) Dc Specifications

    Electrical Specifications Table 7-14. System Reference Clock (BCLK{0/1}) DC Specifications Symbol Parameter Signal Unit Figure Notes Differential Input High Differential 0.150 BCLK_diff_ih Voltage Differential Input Low Differential — -0.150 BCLK_diff_il Voltage Absolute Crossing Point Single (abs) 0.250 0.550 2, 4, 7 cross Ended Relative Crossing Point...

  • Page 67: Jtag And Tap Signals Dc Specifications

    Electrical Specifications Table 7-16. JTAG and TAP Signals DC Specifications Symbol Parameter Units Notes Input Low Voltage — 0.3*VTT Input High Voltage 0.7*VTT — Output Low Voltage — 0.12*V = 500 ohm) TEST Output High Voltage 0.88*V — = 500 ohm) TEST Buffer On Resistance Signals BPM[7:0], TDO, —...

  • Page 68: Processor Asynchronous Sideband Dc Specifications

    Electrical Specifications Table 7-18. Processor Asynchronous Sideband DC Specifications Symbol Parameter Units Notes Input Edge Rate Signals: CAT_ERR_N, 0.05 — V/ns MEM_HOT_C{01/23}_N, PMSYNC, PROCHOT_N, PWRGOOD, RESET_N CMOS1.05 V Signals Input Low Voltage — 0.3*V IL_CMOS1.05v Input High Voltage 0.7*V IH_CMOS1.05v Input Low Voltage —...

  • Page 69: Pci Express* Dc Specifications

    Electrical Specifications Table 7-19. Miscellaneous Signals DC Specifications Symbol Parameter Typical Units Notes PROC_SEL_N Signal Output Absolute Max Voltage — 1.10 1.80 O_ABS_MAX Output Current — — μA SKTOCC_N Signal Output Absolute Max Voltage — 3.30 3.50 O_ABS_MAX Output Max Current —...
  • Page 70 Electrical Specifications Datasheet, Volume 1...

  • Page 71: Processor Land Listing

    Processor Land Listing Processor Land Listing This chapter provides sorted land list. Table 8-1 is a listing of all processor lands ordered alphabetically by land name. Table 8-2 is a listing of all processor landsordered by land number. Datasheet, Volume 1...

  • Page 72: Land Name

    Processor Land Listing Table 8-1. Land Name (Sheet 2 of 45) Table 8-1. Land Name (Sheet 1 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction DDR0_CLK_DP[3] CH22 SSTL BCLK_SELECT[0] BD48 CMOS DDR0_CS_N[0] CN25 SSTL BCLK_SELECT[1]...
  • Page 73 Processor Land Listing Table 8-1. Land Name (Sheet 3 of 45) Table 8-1. Land Name (Sheet 4 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction DDR0_DQ[40] CL31 SSTL DDR0_ECC[3] CF18 SSTL DDR0_DQ[41] CJ31 SSTL DDR0_ECC[4]...
  • Page 74 Processor Land Listing Table 8-1. Land Name (Sheet 5 of 45) Table 8-1. Land Name (Sheet 6 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction DDR1_CLK_DP[3] DC21 SSTL DDR1_DQ[40] DA33 SSTL DDR1_CS_N[0] DB24 SSTL DDR1_DQ[41]...
  • Page 75 Processor Land Listing Table 8-1. Land Name (Sheet 7 of 45) Table 8-1. Land Name (Sheet 8 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction DDR1_ECC[3] DB16 SSTL DDR2_CS_N[4] AA19 SSTL DDR1_ECC[4] DA13 SSTL DDR2_CS_N[5]...
  • Page 76 Processor Land Listing Table 8-1. Land Name (Sheet 9 of 45) Table 8-1. Land Name (Sheet 10 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction DDR2_DQ[43] SSTL DDR2_ECC[6] SSTL DDR2_DQ[44] SSTL DDR2_ECC[7] AA27 SSTL DDR2_DQ[45]...
  • Page 77 Processor Land Listing Table 8-1. Land Name (Sheet 11 of 45) Table 8-1. Land Name (Sheet 12 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction DDR3_CS_N[4] SSTL DDR3_DQ[43] SSTL DDR3_CS_N[5] SSTL DDR3_DQ[44] SSTL DDR3_DQ[00] SSTL...
  • Page 78 Processor Land Listing Table 8-1. Land Name (Sheet 13 of 45) Table 8-1. Land Name (Sheet 14 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction DDR3_ECC[6] SSTL PE_RBIAS AH52 PCIEX3 DDR3_ECC[7] SSTL PE_RBIAS_SENSE AF52 PCIEX3...
  • Page 79 Processor Land Listing Table 8-1. Land Name (Sheet 15 of 45) Table 8-1. Land Name (Sheet 16 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction PE2A_TX_DN[2] AR51 PCIEX3 PE2D_RX_DP[15] AY56 PCIEX3 PE2A_TX_DN[3] AP52 PCIEX3 PE2D_TX_DN[12]...
  • Page 80 Processor Land Listing Table 8-1. Land Name (Sheet 17 of 45) Table 8-1. Land Name (Sheet 18 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction PE3C_RX_DP[10] AF50 PCIEX3 RSVD AB48 PE3C_RX_DP[11] AG49 PCIEX3 RSVD AC29...
  • Page 81 Processor Land Listing Table 8-1. Land Name (Sheet 19 of 45) Table 8-1. Land Name (Sheet 20 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction RSVD BG51 RSVD BR51 RSVD BG53 RSVD BT44 RSVD BG55...
  • Page 82 Processor Land Listing Table 8-1. Land Name (Sheet 21 of 45) Table 8-1. Land Name (Sheet 22 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction RSVD CC55 RSVD CK52 RSVD CD16 RSVD CK54 RSVD CD32...
  • Page 83 Processor Land Listing Table 8-1. Land Name (Sheet 23 of 45) Table 8-1. Land Name (Sheet 24 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction RSVD CT50 RSVD DB42 RSVD CT52 RSVD DB44 RSVD CT56...
  • Page 84 Processor Land Listing Table 8-1. Land Name (Sheet 25 of 45) Table 8-1. Land Name (Sheet 26 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction RSVD TEST1 RSVD TEST2 RSVD TEST3 RSVD TEST4 BA55 RSVD...
  • Page 85 Processor Land Listing Table 8-1. Land Name (Sheet 27 of 45) Table 8-1. Land Name (Sheet 28 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction BA13 AP10 BA15 AP12 BA17 AP14 AP16 BB10 BB12 BB14...
  • Page 86 Processor Land Listing Table 8-1. Land Name (Sheet 29 of 45) Table 8-1. Land Name (Sheet 30 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction BT10 BT12 BT14 BJ11 BT16 BJ13 BJ15 BJ17 BU11 BU13...
  • Page 87 Processor Land Listing Table 8-1. Land Name (Sheet 31 of 45) Table 8-1. Land Name (Sheet 32 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction VCCD_01 CJ21 VCCPLL BY14 VCCD_01 CJ23 VCCPLL CA13 VCCD_01 CJ25...
  • Page 88 Processor Land Listing Table 8-1. Land Name (Sheet 33 of 45) Table 8-1. Land Name (Sheet 34 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction AB14 AK10 AB36 AK12 AB42 AK14 AK16 AC31 AD26 AK42...
  • Page 89 Processor Land Listing Table 8-1. Land Name (Sheet 35 of 45) Table 8-1. Land Name (Sheet 36 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction AU49 BF44 AU51 BG47 AV42 BH58 AV54 BJ55 AV56 BJ57...
  • Page 90 Processor Land Listing Table 8-1. Land Name (Sheet 37 of 45) Table 8-1. Land Name (Sheet 38 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction BW15 CD18 BW17 CD36 CE13 BY24 BY42 CF12 BY58 CF14...
  • Page 91 Processor Land Listing Table 8-1. Land Name (Sheet 39 of 45) Table 8-1. Land Name (Sheet 40 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction CK10 CR11 CK36 CR35 CR47 CR49 CL17 CL43 CT28 CM10...
  • Page 92 Processor Land Listing Table 8-1. Land Name (Sheet 41 of 45) Table 8-1. Land Name (Sheet 42 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction CY50 CY52 DA11 DA41 DA43 DA45 DA47 DA51 DB12 DB32...
  • Page 93 Processor Land Listing Table 8-1. Land Name (Sheet 43 of 45) Table 8-1. Land Name (Sheet 44 of 45) Land Name Land No. Buffer Type Direction Land Name Land No. Buffer Type Direction VSS_VCC_SENSE VSS_VSA_SENSE AF14 VSS_VTTD_SENSE BT42 VTTA AE45 VTTA AE53 VTTA...
  • Page 94 Processor Land Listing Table 8-1. Land Name (Sheet 45 of 45) Land Name Land No. Buffer Type Direction VTTA AM54 VTTA AU53 VTTA CA53 VTTA CC45 VTTA CG55 VTTA CJ49 VTTA CR45 VTTA CR51 VTTA DA49 VTTA VTTA VTTD AF22 VTTD AF24 VTTD...

  • Page 95: Land Number

    Processor Land Listing Table 8-2. Land Number (Sheet 1 of 45) Table 8-2. Land Number (Sheet 2 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction DDR3_DQ[33] SSTL AA55 DDR3_MA[13] SSTL RSVD DDR3_WE_N SSTL DDR3_BA[0] SSTL...
  • Page 96 Processor Land Listing Table 8-2. Land Number (Sheet 3 of 45) Table 8-2. Land Number (Sheet 4 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction AC39 RSVD AE23 RSVD AC41 DDR2_DQ[12] SSTL AE25 RSVD AC43...
  • Page 97 Processor Land Listing Table 8-2. Land Number (Sheet 5 of 45) Table 8-2. Land Number (Sheet 6 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction AF52 PE_RBIAS_SENSE PCIEX3 AH50 PE3C_RX_DN[10] PCIEX3 AF54 AH52 PE_RBIAS PCIEX3...
  • Page 98 Processor Land Listing Table 8-2. Land Number (Sheet 7 of 45) Table 8-2. Land Number (Sheet 8 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction AL17 AL43 AP10 AL45 AP12 AL47 RSVD AP14 AL49 AP16...
  • Page 99 Processor Land Listing Table 8-2. Land Number (Sheet 9 of 45) Table 8-2. Land Number (Sheet 10 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction AT48 BIST_ENABLE CMOS AW15 AT50 TESTHI_AT50 CMOS AW17 AT52 AT54...
  • Page 100 Processor Land Listing Table 8-2. Land Number (Sheet 11 of 45) Table 8-2. Land Number (Sheet 12 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction DMI_TX_DP[2] PCIEX BC15 RSVD BC17 DMI_RX_DP[1] PCIEX DMI_RX_DP[3] PCIEX BC43...
  • Page 101 Processor Land Listing Table 8-2. Land Number (Sheet 13 of 45) Table 8-2. Land Number (Sheet 14 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction BE57 RSVD BH46 RSVD BH48 TESTHI_BH48 Open Drain BH50 RSVD BF10...
  • Page 102 Processor Land Listing Table 8-2. Land Number (Sheet 15 of 45) Table 8-2. Land Number (Sheet 16 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction BL13 BN55 RSVD BL15 BN57 RSVD BL17 BL43 RSVD BP10...
  • Page 103 Processor Land Listing Table 8-2. Land Number (Sheet 17 of 45) Table 8-2. Land Number (Sheet 18 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction BT44 RSVD BW11 BT46 BW13 BT48 BW15 BT50 BW17 BT52...
  • Page 104 Processor Land Listing Table 8-2. Land Number (Sheet 19 of 45) Table 8-2. Land Number (Sheet 20 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction CA49 RSVD VCCD_23 CA51 RSVD VCCD_23 CA53 VTTA VCCD_23 CA55...
  • Page 105 Processor Land Listing Table 8-2. Land Number (Sheet 21 of 45) Table 8-2. Land Number (Sheet 22 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction CC29 CE11 DDR0_DQS_DP[03] SSTL CE13 CC31 DDR0_DQ[33] SSTL CE15 DDR0_ECC[0]...
  • Page 106 Processor Land Listing Table 8-2. Land Number (Sheet 23 of 45) Table 8-2. Land Number (Sheet 24 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction CF44 RSVD CH28 DDR0_ODT[2] SSTL CF46 RSVD CH30 DDR0_DQ[45] SSTL...
  • Page 107 Processor Land Listing Table 8-2. Land Number (Sheet 25 of 45) Table 8-2. Land Number (Sheet 26 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction CK10 CL45 RSVD CK12 DDR0_DQ[16] SSTL CL47 RSVD CK14 DDR0_DQS_DP[02]...
  • Page 108 Processor Land Listing Table 8-2. Land Number (Sheet 27 of 45) Table 8-2. Land Number (Sheet 28 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction CN29 DDR0_WE_N SSTL CP58 RSVD DDR1_DQ[20] SSTL CN31 RSVD CN33...
  • Page 109 Processor Land Listing Table 8-2. Land Number (Sheet 29 of 45) Table 8-2. Land Number (Sheet 30 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction CT34 DDR1_DQ[34] SSTL CV10 DDR1_DQ[23] SSTL CT36 DDR1_DQ[52] SSTL CV12...
  • Page 110 Processor Land Listing Table 8-2. Land Number (Sheet 31 of 45) Table 8-2. Land Number (Sheet 32 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction CW39 RSVD CW41 DDR_SDA_C01 ODCMOS DDR3_MA[10] SSTL CW43 RSVD CW45...
  • Page 111 Processor Land Listing Table 8-2. Land Number (Sheet 33 of 45) Table 8-2. Land Number (Sheet 34 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction DA51 DC35 DDR1_DQ[42] SSTL DA53 RSVD DC37 DDR1_DQ[61] SSTL DA55...
  • Page 112 Processor Land Listing Table 8-2. Land Number (Sheet 35 of 45) Table 8-2. Land Number (Sheet 36 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction DE33 RSVD DE35 DDR1_DQ[47] SSTL DE37 DDR1_DQ[56] SSTL DDR3_DQS_DP[02] SSTL...
  • Page 113 Processor Land Listing Table 8-2. Land Number (Sheet 37 of 45) Table 8-2. Land Number (Sheet 38 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction DDR3_DQ[49] SSTL DDR3_DQ[15] SSTL DDR3_DQ[61] SSTL RSVD VCCD_23 PE1A_TX_DP[0] PCIEX3...
  • Page 114 Processor Land Listing Table 8-2. Land Number (Sheet 39 of 45) Table 8-2. Land Number (Sheet 40 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction RSVD DDR3_DQ[44] SSTL PE1A_TX_DN[1] PCIEX3 RSVD PE1A_TX_DN[3] PCIEX3 DDR3_CS_N[4] SSTL...
  • Page 115 Processor Land Listing Table 8-2. Land Number (Sheet 41 of 45) Table 8-2. Land Number (Sheet 42 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction VCCD_23 VCCD_23 DDR3_CKE[3] SSTL DDR3_DQ[51] SSTL DDR3_DQ[30] SSTL DDR3_DQS_DP[03] SSTL...
  • Page 116 Processor Land Listing Table 8-2. Land Number (Sheet 43 of 45) Table 8-2. Land Number (Sheet 44 of 45) Land No. Land Name Buffer Type Direction Land No. Land Name Buffer Type Direction DDR2_DQS_DN[00] SSTL VCCD_23 VCCD_23 DDR2_DQ[00] SSTL VCCD_23 PE3D_TX_DP[15] PCIEX3 PE3C_TX_DN[8]...
  • Page 117 Processor Land Listing Table 8-2. Land Number (Sheet 45 of 45) Land No. Land Name Buffer Type Direction PE2A_RX_DN[3] PCIEX3 DDR2_DQ[45] SSTL DDR23_RCOMP[2] Analog RSVD DDR2_ODT[3] SSTL DDR2_ODT[0] SSTL DDR2_CLK_DN[1] SSTL DDR2_CLK_DN[0] SSTL DDR2_ECC[2] SSTL RSVD DDR2_DQ[57] SSTL PE3D_TX_DP[13] PCIEX3 PE3C_TX_DP[11] PCIEX3 RSVD...
  • Page 118 Processor Land Listing Datasheet, Volume 1...

  • Page 119: Package Mechanical Specifications

    Package Mechanical Specifications Package Mechanical Specifications ® For mechanical specifications and design guidelines refer to the Intel Core™ i7 Processor Family for the LGA-2011 Socket Thermal Mechanical Specification and Design Guide. § Datasheet, Volume 1...
  • Page 120 Package Mechanical Specifications Datasheet, Volume 1...

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