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TMS320C642 Series
Texas Instruments TMS320C642 Series Manuals
Manuals and User Guides for Texas Instruments TMS320C642 Series. We have
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Texas Instruments TMS320C642 Series manuals available for free PDF download: User Manual
Texas Instruments TMS320C642 Series User Manual (57 pages)
DSP DDR2 Memory Controller
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 0.47 MB
Table of Contents
Table of Contents
3
Preface
6
Introduction
7
Purpose of the Peripheral
7
Features
7
Functional Block Diagram
8
Supported Use Case Statement
8
Industry Standard(S) Compliance Statement
8
Data Paths to DDR2 Memory Controller
8
Peripheral Architecture
9
Clock Control
9
DDR2 Memory Controller Clock Block Diagram
9
Memory Map
10
PLLC2 Configuration
10
Signal Descriptions
11
DDR2 Memory Controller Signals
11
DDR2 Memory Controller Signal Descriptions
11
Protocol Description(S)
12
DDR2 SDRAM Commands
12
Truth Table for DDR2 SDRAM Commands
12
Refresh Command
13
DCAB Command
14
DEAC Command
15
ACTV Command
16
DDR2 READ Command
17
DDR2 WRT Command
18
DDR2 MRS and EMRS Command
19
Memory Width and Byte Alignment
20
Byte Alignment (Little-Endian Mode)
20
Addressable Memory Ranges
20
Endianness Support
21
32-Bit External Memory
21
Address Mapping
22
Bank Configuration Register Fields for Address Mapping
22
Logical Address-To-DDR2 SDRAM Address Map for 32-Bit SDRAM
23
Logical Address-To-DDR2 SDRAM Address Map for 16-Bit SDRAM
23
Logical Address-To-DDR2 SDRAM Address Map
24
DDR2 SDRAM Column, Row, and Bank Access
25
DDR2 Memory Controller Interface
26
DDR2 Memory Controller FIFO Block Diagram
26
DDR2 Memory Controller FIFO Description
26
Refresh Scheduling
29
2.10 Self-Refresh Mode
29
Refresh Urgency Levels
29
2.11 Reset Considerations
30
DDR2 Memory Controller Reset Block Diagram
30
Reset Sources
30
2.12 VTP IO Buffer Calibration
31
2.13 Auto-Initialization Sequence
31
DDR2 SDRAM Configuration by MRS Command
32
DDR2 SDRAM Configuration by EMRS(1) Command
32
2.14 Interrupt Support
34
2.15 DMA Event Support
34
2.16 Power Management
34
DDR2 Memory Controller Power Sleep Controller Diagram
34
2.17 Emulation Considerations
35
Supported Use Cases
36
Connecting the DDR2 Memory Controller to DDR2 Memory
36
Configuring Memory-Mapped Registers to Meet DDR2-400 Specification
36
Connecting DDR2 Memory Controller for 32-Bit Connection
37
Connecting DDR2 Memory Controller for 16-Bit Connection
37
SDRAM Bank Configuration Register (SDBCR) Configuration
38
DDR2 Memory Refresh Specification
38
SDRAM Refresh Control Register (SDRCR) Configuration
38
SDRAM Timing Register (SDTIMR) Configuration
39
SDRAM Timing Register 2 (SDTIMR2) Configuration
39
DDR PHY Control Register (DDRPHYCR) Configuration
40
DDR2 Memory Controller Registers
41
DDR2 Memory Controller Registers Relative to Base Address 2000 0000H
41
DDR2 Memory Controller Registers Relative to Base Address 01C4 2000H
41
DDR2 Memory Controller Registers Relative to Base Address 01C4 0000H
41
SDRAM Status Register (SDRSTAT)
42
SDRAM Status Register (SDRSTAT) Field Descriptions
42
SDRAM Bank Configuration Register (SDBCR)
43
SDRAM Bank Configuration Register (SDBCR) Field Descriptions
43
SDRAM Refresh Control Register (SDRCR)
45
SDRAM Refresh Control Register (SDRCR) Field Descriptions
45
SDRAM Timing Register (SDTIMR)
46
SDRAM Timing Register (SDTIMR) Field Descriptions
46
SDRAM Timing Register 2 (SDTIMR2)
47
SDRAM Timing Register 2 (SDTIMR2) Field Descriptions
47
Peripheral Bus Burst Priority Register (PBBPR)
48
Peripheral Bus Burst Priority Register (PBBPR) Field Descriptions
48
Interrupt Raw Register (IRR)
49
Interrupt Raw Register (IRR) Field Descriptions
49
Interrupt Masked Register (IMR)
50
Interrupt Masked Register (IMR) Field Descriptions
50
Interrupt Mask Set Register (IMSR)
51
Interrupt Mask Set Register (IMSR) Field Descriptions
51
Interrupt Mask Clear Register (IMCR)
52
Interrupt Mask Clear Register (IMCR) Field Descriptions
52
DDR PHY Control Register (DDRPHYCR)
53
DDR PHY Control Register (DDRPHYCR) Field Descriptions
53
VTP IO Control Register (VTPIOCR)
54
VTP IO Control Register (VTPIOCR) Field Descriptions
54
DDR VTP Register (DDRVTPR)
55
DDR VTP Enable Register (DDRVTPER)
55
DDR VTP Register (DDRVTPR) Field Descriptions
55
DDR VTP Enable Register (DDRVTPER) Field Descriptions
55
Appendix A Revision History
56
Document Revision History
56
Important Notice
57
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Texas Instruments TMS320C642 Series User Manual (41 pages)
DSP Inter-Integrated Circuit (I2C) Peripheral
Brand:
Texas Instruments
| Category:
Computer Hardware
| Size: 0.24 MB
Table of Contents
Table of Contents
3
Preface
6
Introduction
7
Purpose of the Peripheral
7
Features
7
Functional Block Diagram
8
Industry Standard(S) Compliance Statement
8
I2C Peripheral Block Diagram
8
Peripheral Architecture
9
Bus Structure
9
Multiple I2C Modules Connected
9
Clock Generation
10
Clocking Diagram for the I2C Peripheral
10
Clock Synchronization
11
Signal Descriptions
11
Synchronization of Two I2C Clock Generators During Arbitration
11
START and STOP Conditions
12
Bit Transfer on the I2C-Bus
12
I2C Peripheral START and STOP Conditions
12
Serial Data Formats
13
I2C Peripheral Data Transfer
13
I2C Peripheral 7-Bit Addressing Format (FDF = 0, XA = 0 in ICMDR)
13
I2C Peripheral 10-Bit Addressing Format with Master-Transmitter Writing to Slave-Receiver (FDF = 0, XA = 1 in ICMDR)
14
I2C Peripheral Free Data Format (FDF = 1 in ICMDR)
14
I2C Peripheral 7-Bit Addressing Format with Repeated START Condition (FDF = 0, XA = 0 in ICMDR)
14
Endianness Considerations
15
Operating Modes
15
Operating Modes of the I2C Peripheral
15
NACK Bit Generation
16
Ways to Generate a NACK Bit
16
2.10 Arbitration
17
Arbitration Procedure between Two Master-Transmitters
17
2.11 Reset Considerations
18
2.12 Initialization
18
2.13 Interrupt Support
21
2.14 DMA Events Generated by the I2C Peripheral
21
2.15 Power Management
21
Descriptions of the I2C Interrupt Events
21
2.16 Emulation Considerations
22
Registers
22
Inter-Integrated Circuit (I2C) Registers
22
I2C Own Address Register (ICOAR)
23
I2C Own Address Register (ICOAR) Field Descriptions
23
I2C Interrupt Mask Register (ICIMR)
24
I2C Interrupt Mask Register (ICIMR) Field Descriptions
24
I2C Interrupt Status Register (ICSTR)
25
I2C Interrupt Status Register (ICSTR) Field Descriptions
25
I2C Clock Divider Registers (ICCLKL and ICCLKH)
28
I2C Clock Low-Time Divider Register (ICCLKL)
28
I2C Clock High-Time Divider Register (ICCLKH)
28
I2C Clock Low-Time Divider Register (ICCLKL) Field Descriptions
28
I2C Clock High-Time Divider Register (ICCLKH) Field Descriptions
28
I2C Data Count Register (ICCNT)
29
I2C Data Count Register (ICCNT) Field Descriptions
29
I2C Data Receive Register (ICDRR)
30
I2C Slave Address Register (ICSAR)
30
I2C Data Receive Register (ICDRR) Field Descriptions
30
I2C Slave Address Register (ICSAR) Field Descriptions
30
I2C Data Transmit Register (ICDXR)
31
I2C Data Transmit Register (ICDXR) Field Descriptions
31
I2C Mode Register (ICMDR)
32
I2C Mode Register (ICMDR) Field Descriptions
32
Master-Transmitter/Receiver Bus Activity Defined by RM, STT, and STP Bits
34
Block Diagram Showing the Effects of the Digital Loopback Mode (DLB) Bit
35
How the MST and FDF Bits Affect the Role of TRX Bit
35
I2C Interrupt Vector Register (ICIVR)
36
I2C Interrupt Vector Register (ICIVR) Field Descriptions
36
I2C Extended Mode Register (ICEMDR)
37
I2C Extended Mode Register (ICEMDR) Field Descriptions
37
I2C Prescaler Register (ICPSC)
38
I2C Prescaler Register (ICPSC) Field Descriptions
38
I2C Peripheral Identification Register (ICPID1)
39
I2C Peripheral Identification Register (ICPID2)
39
I2C Peripheral Identification Register 1 (ICPID1)
39
I2C Peripheral Identification Register 2 (ICPID2)
39
I2C Peripheral Identification Register 1 (ICPID1) Field Descriptions
39
I2C Peripheral Identification Register 2 (ICPID2) Field Descriptions
39
Appendix A Revision History
40
Document Revision History
40
Important Notice
41
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