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Introduction
1 Introduction
This user's guide defines the power distribution network (PDN) between the TPS6594-Q1 and LP8764-Q1
devices and the DRA821 processor. This document describes the platform power resource connections, digital
control connections, and PMIC sequencing settings to support the different processor state transitions. The
PMIC default non-volatile memory (NVM) settings, internal state transitions, and power sequences are also
defined in this document. This user's guide does not provide information about the electrical characteristics,
external components, package, or the functionality of the PMICs or processor. For such information and the full
register maps, refer to the data sheet for each device. In the event of any inconsistency between the official
specification and any user's guide, application report, or other referenced material, the data sheet specification is
the definitive source.
2 Device Versions
There are different versions of the TPS6594-Q1 and LP8764-Q1 devices available with unique NVM settings
to support different processor solutions. The unique NVM settings for each PMIC device are optimized per
PDN design to support different processors, processing loads, SDRAM types, system functional safety levels,
and end product features - such as low power modes, processor interface levels, SD Card, and so forth. The
NVM settings can be distinguished using the TI_NVM_ID register. In this user guide, each PMIC device is
distinguished by the TI orderable part number, TI_NVM_ID, and TI_NVM_REV values listed in
Table 2-1. TPS6594-Q1 and LP8764-Q1 NVM Settings and Orderable Part Numbers
PDN USE CASE
(1)
•
Up to 4.25 A
on the CORE rail
(1)
•
Up to 4.25 A
on the CPU rails
(1)
•
Up to 3.4 A
on the SDRAM, with support for
LPDDR4
•
Supports Functional Safety up to ASIL-D level
•
Supports low power modes, including MCU-
only, GPIO Retention, and DDR Retention
states
•
Supports I/O level of 3.3 V or 1.8 V
•
Supports use of SD card
(1)
TI recommends having 15% margin between the maximum expected load current and the maximum current allowed per each PMIC
output rail.
2
Powering DRA821 with TPS6594-Q1 and LP8764-Q1
Orderable Part Number
TPS6594141B
LP876441B1
Copyright © 2022 Texas Instruments Incorporated
Device Mode
TI_NVM_ID
0x1B
Primary
Secondary
0xB1
SLVUBY7A – OCTOBER 2020 – REVISED OCTOBER 2022
www.ti.com
Table
2-1.
TI_NVM_REV
0x01
0x01
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