Intel Itanium 9150M Manuals

Manuals and User Guides for Intel Itanium 9150M. We have 2 Intel Itanium 9150M manuals available for free PDF download: Manual

INTEL Itanium 9150M Manual (420 pages)

Architecture Software Developer's manual revision 2.3

Brand: INTEL | Category: Software | Size: 3.01 MB

Table of Contents

4
- 1 About this Manual
  
  10
- 2 Instruction Reference
  
  20
  - Instruction Page Font Conventions
    20
  - Register File Notation
    21
    
    Instruction Descriptions
    22
  - Pervasive Conditions Not Included in Instruction Description Code
    22
  - Add Pointer
    24
  - Stack Frame
    25
  - Branch Types
    29
  - Operation of Br.ctop and Br.cexit
    32
  - Operation of Br.wtop and Br.wexit
    33
  - Branch Cache Deallocation Hint
    33
  - Branch Whether Hint
    34
  - Sequential Prefetch Hint
    34
  - Long Branch Types
    39
  - IP-Relative Branch Predict Whether Hint
    41
  - Indirect Branch Predict Whether Hint
    41
  - Importance Hint
    41
  - ALAT Clear Completer
    44
Table of Contents

45
- ].Nat
  
  47
- Natval
  
  66
  - Specified Pc Mnemonic Values
    65
- If (Fail)
  
  70
  - If (Psr.tb)
    72
    
    Taken_Branch_Trap()
    72
  - IP = IP + Sign_Ext
    72
    
    (!Psr.it && Unimplemented_Physical_Address(IP)))
    72
    
    ((Psr.it && Unimplemented_Virtual_Address(IP, Psr.VM))
    72
    
    If (!Impl_Uia_Fault_Supported() && 21 << 4), 25)
    72
    
    Unimplemented_Instruction_Address_Trap(0, IP)
    72
  - Speculation_Fault
    72
  - Taken_Branch = 1
    72
  - Floating-Point Class Relations
    73
  - Floating-Point Classes
    73
  - Floating-Point Comparison Relations
    76
  - Floating-Point Comparison Types
    76
  - Fetch and Add Semaphore Types
    83
  - Floating-Point Merge Negative Sign Operation
    89
  - Floating-Point Merge Sign and Exponent Operation
    89
  - Floating-Point Merge Sign Operation
    89
  - Floating-Point MIX Left
    92
  - Floating-Point MIX Left-Right
    92
  - Floating-Point MIX Right
    92
  - Floating-Point Pack
    105
  - Floating-Point Parallel Comparison Relations
    110
  - Floating-Point Parallel Comparison Results
    110
  - Floating-Point Parallel Merge Negative Sign Operation
    120
  - Floating-Point Parallel Merge Sign Operation
    120
  - Floating-Point Parallel Merge Sign and Exponent Operation
    121
  - Floating-Point Swap
    146
  - Floating-Point Swap Negate Left
    146
  - Floating-Point Swap Negate Right
    147
  - Floating-Point Sign Extend Left
    148
  - Floating-Point Sign Extend Right
    148
  - Function of Getf.exp
    152
  - Function of Getf.sig
    152
  - Hint Immediates
    154
  - Load Types
    160
  - Sz Completers
    160
  - Load Hints
    161
  - FP Load Types
    166
  - Fsz Completers
    166
  - Lftype Mnemonic Values
    173
  - Lfhint Mnemonic Values
    174
  - MIX Examples
    179
  - Move to BR Whether Hints
    183
  - Indirect Register File Mnemonics
    189
  - Mux Permutations for 8-Bit Elements
    199
  - Mux2 Examples (16-Bit Elements)
    200
  - Pack Operation
    204
  - Pack Saturation Limits
    204
  - Parallel Add Examples
    206
  - Parallel Add Saturation Completers
    206
  - Parallel Add Saturation Limits
    206
  - Parallel Average Example
    210
  - Parallel Average with Round Away from Zero Example
    211
  - Parallel Average Subtract Example
    213
  - Parallel Compare Examples
    215
  - Pcmp Relations
    215
  - Parallel Multiply Operation
    222
  - Parallel Multiply and Shift Right Operation
    223
  - Parallel Multiply and Shift Right Shift Options
    223
  - Faults for Regular_Form and Fault_Form Probe Instructions
    227
  - Parallel Sum of Absolute Difference Example
    229
  - Parallel Shift Left Examples
    231
  - Parallel Subtract Examples
    236
  - Parallel Subtract Saturation Completers
    236
  - Parallel Subtract Saturation Limits
    236
  - Function of Setf.exp
    251
  - Function of Setf.sig
    251
  - Shift Left and Add Pointer
    255
  - Store Types
    260
  - Store Hints
    261
  - Xsz Mnemonic Values
    267
  - Test Bit Relations for Normal and Unc Tbits
    270
  - Test Bit Relations for Parallel Tbits
    270
  - Test Feature Features Assignment
    272
  - Test Feature Relations for Normal and Unc
    272
  - Test Feature Relations for Parallel
    272
  - Test Nat Relations for Normal and Unc Tnats
    275
  - Test Nat Relations for Parallel Tnats
    275
  - Memory Exchange Size
    283
- 3 Pseudo-Code Functions
  
  290
- 4 Instruction Formats
  
  302
- 5 Resource and Dependency Semantics
  
  380
  - Reading and Writing Resources
    380
  - Dependencies and Serialization
    380
  - Resource and Dependency Table Format Notes
    381
  - Semantics of Dependency Codes
    382
    
    RAW Dependency Table
    383
    
    Special Case Instruction Rules
    383
  - RAW Dependencies Organized by Resource
    384
    
    WAW Dependency Table
    392
  - WAW Dependencies Organized by Resource
    392
    
    WAR Dependency Table
    396
  - WAR Dependencies Organized by Resource
    396
  - Instruction Classes
    398

Intel Itanium 9150M Manual (108 pages)

Dual-Core Intel Itanium Processor 9000 and 9100 Series

Brand: Intel | Category: Computer Hardware | Size: 1.74 MB

Table of Contents
3
Revision History
8
Product Features
9
1 Introduction

11
- Overview
  11
- Processor Abstraction Layer
  11
- Mixing Processors of Different Frequencies and Cache Sizes
  12
- Terminology
  12
- State of Data
  12
- Reference Documents
  13
2 Electrical Specifications

15
3 Pinout Specifications

35
4 Mechanical Specifications

65
5 Thermal Specifications

75
6 System Management Feature Specifications

79
- System Management Bus
  79
  - System Management Bus Interface
    79
  - System Management Interface Signals
    79
- System Management Interface Signal Descriptions
  79
  - Logical Schematic of Smbus Circuitry
    80
    
    Smbus Device Addressing
    81
- Thermal Sensing Device Smbus Addressing on the Dual-Core Intel
  81
  - Processor Information ROM
    82
- EEPROM Smbus Addressing on the Dual-Core Intel
  82
- Processor Information ROM Format
  82
  - Scratch EEPROM
    85
- Processor Information ROM and Scratch EEPROM Supported Smbus Transactions
  85
- Current Address Read Smbus Packet
  85
- Thermal Sensing Device
  86
- Random Address Read Smbus Packet
  86
- Byte Write Smbus Packet
  86
- Thermal Sensing Device Supported Smbus Transactions
  87
- Write Byte Smbus Packet
  87
- Read Byte Smbus Packet
  87
- Send Byte Smbus Packet
  87
- Receive Byte Smbus Packet
  87
- ARA Smbus Packet
  87
- Thermal Sensing Device Registers
  88
  - Thermal Reference Registers
    88
- Command Byte Bit Assignment
  88
  - Thermal Limit Registers
    89
  - Status Register
    89
  - Configuration Register
    89
- Thermal Sensing Device Status Register
  89
- Thermal Sensing Device Configuration Register
  89
  - Conversion Rate Register
    90
- Thermal Sensing Device Conversion Rate Register
  90
- Signals Reference
  91
- Alphabetical Signals Reference
  91
  - A[49:3]# (I/O)
    91
  - A20M# (I)
    91
  - Ads# (I/O)
    91
  - Ap[1:0]# (I/O)
    91
  - Asz[1:0]# (I/O)
    91
  - Attr[3:0]# (I/O)
    92
  - Bclkp/Bclkn (I)
    92
  - Be[7:0]# (I/O)
    92
- Address Space Size
  92
- Effective Memory Type Signal Encoding
  92
  - Berr# (I/O)
    93
- Special Transaction Encoding on Byte Enables
  93
  - Binit# (I/O)
    94
  - Bnr# (I/O)
    94
  - Bpm[5:0]# (I/O)
    94
  - Bpri# (I)
    94
  - BR[0]# (I/O) and BR[3:1]# (I)
    94
  - Breq[3:0]# (I/O)
    95
- BR0# (I/O), BR1#, BR2#, BR3# Signals for 2P Rotating Interconnect
  95
- BR0# (I/O), BR1#, BR2#, BR3# Signals for 4P Rotating Interconnect
  95
- BR[3:0]# Signals and Agent Ids
  95
  - Ccl# (I/O)
    96
  - Cpupres# (O)
    96
  - D[127:0]# (I/O)
    96
  - D/C# (I/O)
    96
  - Dbsy# (I/O)
    96
  - Dbsy_C1# (O)
    96
  - Dbsy_C2# (O)
    96
  - Defer# (I)
    96
  - Den# (I/O)
    97
  - Dep[15:0]# (I/O)
    97
  - Dhit# (I)
    97
- DID[9:0]# Encoding
  97
  - Dps# (I/O)
    98
  - Drdy# (I/O)
    98
  - Drdy_C1# (O)
    98
  - Drdy_C2# (O)
    98
  - Dsz[1:0]# (I/O)
    98
  - Exf[4:0]# (I/O)
    98
- Itanium ® Processor
  98
- Extended Function Signals
  98
  - Fcl# (I/O)
    99
  - Ferr# (O)
    99
  - Gseq# (I)
    99
  - HIT# (I/O) and HITM# (I/O)
    99
  - Ids# (I)
    99
  - Ignne# (I)
    99
  - Init# (I)
    99
  - Int (I)
    100
  - Len[2:0]# (I/O)
    100
  - Lint[1:0] (I)
    100
    
    Lock# (I/O)
    100
- Length of Data Transfers
  100
  - Nmi (I)
    101
  - Own# (I/O)
    101
  - Pmi# (I)
    101
  - Pwrgood (I)
    101
  - Req[5:0]# (I/O)
    101
  - Reset# (I)
    102
  - Rp# (I/O)
    102
- Transaction Types Defined by Reqa#/Reqb# Signals
  102
  - Rsp# (I)
    103
  - Sbsy# (I/O)
    103
  - Sbsy_C1# (O)
    103
  - Sbsy_C2# (O)
    103
  - Splck# (I/O)
    103
  - Stbn[7:0]# and Stbp[7:0]# (I/O)
    103
  - Tck (I)
    104
  - Tdi (I)
    104
  - Tdo (O)
    104
  - Thrmtrip# (O)
    104
  - Thrmalert# (O)
    104
  - Tms (I)
    104
  - Tnd# (I/O)
    104
- Stbp[7:0]# and Stbn[7:0]# Associations
  104
  - Trdy# (I)
    105
  - Trst# (I)
    105
  - Wsnp# (I/O)
    105
  - Signal Summaries
    105
- Output Signals
  105
- Input Signals
  105
- Input/Output Signals (Single Driver)
  106
- Input/Output Signals (Multiple Driver)
  107

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Intel Itanium 9150M Manuals

INTEL Itanium 9150M Manual (420 pages)

Table of Contents

Table of Contents

1 About this Manual

2 Instruction Reference

Table of Contents

].Nat

Natval

If (Fail)

3 Pseudo-Code Functions

4 Instruction Formats

5 Resource and Dependency Semantics

Intel Itanium 9150M Manual (108 pages)

Table of Contents

1 Introduction

2 Electrical Specifications

3 Pinout Specifications

4 Mechanical Specifications

5 Thermal Specifications

6 System Management Feature Specifications

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Intel Categories