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iSBC 432/100
Preparation for Use
Table 2-2. Jumper Selectable Options (Cont'd.)
Function
Fig. 5-1
I
Fig. 5-2
I
Grid Ref.
Grid Ref.
Bus Arbitration
1B7
2A4
User Selectable Inputs
1B6
4C5
GDP Initialization
1C5
4D6
Serial
1/0
Port
1C4
3C2
*Default jumper configured at the factory.
Study table 2-2 carefully while making reference to
figures 5-1 and 5-2. If the default (factory con-
figured) jumper configuration is appropriate for a
particular function, no further action is required for
that function. If, however, a different configuration
is required, remove the default jumper(s) and/ or
install optional jumper(s) as specified. For most
options, the information in table 2-2 is sufficient for
proper configuration. Additional information, where
necessary, is contained in the following paragraphs.
2.9 1/0 ACCESS
All on-board 1/0 devices are accessible only from the
Multibus bus. The selection of an 1/0 base address is
performed by the user as described in table 2-2. By
moving the address selection jumper, the most
significant four 1/0 address bits are fixed as:
Description
Default jumper 81-82* routes the Bus Priority Out signal BPRO/
to the Multibus bus. (Refer to table 2-4.) This jumper should
always be connected when the processor board is inserted in
an lntellec system or used with a serial priority bus resolution
scheme.
The Common Bus Request signal (CBRQ) from the Multibus
bus is not presently used.
Three user selectable jumpers are available for system
confiQuration inputs. These three inputs are read throuqh the
processor status port. These inputs ·appear on the three most
significant data lines as follows:
Port
Associated
Data Bit
Jumper
=0
=1
07
40-41 *
remove jumper
install jumper*
06
38-39*
remove jumper
install jumper*
05
36-37*
remove jumper
install jumper*
In normal operation (default jumper 43-44*), the GDP is
initialized when a Multibus master writes an initialization
pattern to the processor control 1/0 port and also when the
Multibus INIT I signal is activated. The GDP is held in the
initialized state until the Multibus master subsequently
rewrites the
110
port.
The serial
1/0
port has three jumper selectable options.
Jumper 31-32 provides 1/0 loopback for testing. This jumper
should not be connected in normal operation; 27-28* provides
an automatic data set ready response when the data terminal
ready signal is asserted; 29-30* provides an automatic clear-to-
send response when the request-to-send signal is asserted.
User configuration of these jumpers is terminal dependent.
A7
A6
AS
A4
Hex
Jumper
0
0
0
1
1
79-80
0
0
1
0
2
77-78
0
0
1
1
3
75-76
0
1
0
0
4
73-74
0
1
0
1
5
71-72
0
1
1
0
6
69-70
0
1
1
1
7
67-68
The least significant four bits of the 1/0 address are
determined by the individual 1/0 port; a list of 1/0
addresses and corresponding I/O ports is given in
table 3-1. The processor ID register always resides at
Multibus 1/0 address OOH and cannot be relocated.
Note that all Multibus 1/0 addresses generated by
the iSBC 432/ 100
board
are
even, i.e., the least-
significant address bit is always zero. In addition, all
Multibus addresses (110 or memory) are generated
using the on-board off set register, as discussed in
paragraph 4-5.
2-3
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