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Programming Information
iSBC 432/100
Table 3-1. iSBC 432/ 100™ 1/0 Address Assignments
1/0 Address
R/W
Description
00
R
Processor ID Register
XO
R/W
8253 PIT
Process Clock Timer
Read:
Counter 0
Write:
Counter O (load count)
X2
R/W
Process Clock Timer
'Read:
Counter 1
Write:
Counter 1 (load count)
X4
R/W
Baud Rate Generator
Read:
Counter 2
Write:
Counter 2 (load count)
X6
R/W
Read:
None
Write:
Control
X8
R/W
8251A USART
Read:
Data (J1)
Write:
Data (J1)
XA
R/W
Read:
Status
Write:
Mode or Command
xc
w
Memory Address Offset Register (contains an
8-bit memory offset for all memory addressing
operations)
XE
R
Processor Status Register
bit#
description
0
processor initialization hold
1
interrupt pending
2
GDP accesses stopped
3
stop command active
4
fatal error
5-7
user selectable jumpers
XE
w
Processor Control
bit#
description
0
release processor from
initialized state
1
issue Multibus interrupt
2
issue interprocessor com-
munication request
3
stop GDP accesses
4
issue alarm signal
Note: Xis jumper selectable (1-7) as described in table 2-2.
written into the USART, sync characters or com-
mand instructions may be inserted. The Mode
instruction word defines the following:
b. For Asynchronous Mode:
(1) Baud rate factor (Xl, X16, or X64)
(2) Character length
a.
For Synchronous Mode:
( 1) Character length
3-2
(2) Parity enable
(3) Even/ odd parity generation and check
(4) External sync detect (not supported by the
iSBC 432/100 board)
(5) Single- or double-character sync
(3) Parity enable
(4) Even/odd parity generation and check
(5) Number of stop bits
Instruction word and data transmission formats for
synchronous and asynchronous modes are shown in
figures 3-1 through 3-4.
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