Direct Cache Access (Dca) - Intel XL710-Q2 User Manual

Low Latency Interrupts (LLI)
The LLI feature enables the network device to by-pass the configured interrupt moderation scheme based on
the type of data being received. It configures which arriving TCP packets trigger an immediate interrupt,
enabling the system to handle the packet more quickly. Reduced data latency enables some applications to
gain faster access to network data.
NOTE: When LLI is enabled, system CPU utilization may increase.
LLI Options:
You may evoke LLI for data packets containing a TCP PSH flag in the header or for specified TCP ports.
Use for packets
with TCP PSH flag:
Use for these TCP
ports:

Direct Cache Access (DCA)

Direct Cache Access enables a capable I/O device such as a network controller to activate a pre-fetch engine
in the CPU that loads arriving packet data into the CPU cache for immediate access by the network stack
process. This reduces the number of memory access operations required to process each packet, reducing
CPU load and increasing throughput.
DCA takes advantage of high-speed cache and eliminates processor cycles required to read packet headers
and descriptors from system memory.
NOTE: DCA requires support from the I/O device, system chipset, and CPU.
Direct Memory Access (DMA) Coalescing
DMA (Direct Memory Access) allows the network device to move packet data directly to the system's
memory, reducing CPU utilization. However, the frequency and random intervals at which packets arrive do
not allow internal system components to enter energy-saving states. DMA Coalescing allows the NIC to
collect packets before it initiates a DMA event. This may increase network latency but also increases the
chances that the system will consume less energy.
Higher DMA Coalescing values result in more energy saved but may increase your system's network latency.
If you enable DMA Coalescing, you should also set the Interrupt Moderation Rate to 'Minimal'. This minimizes
the latency impact imposed by DMA Coalescing and results in better peak network throughput performance.
You must enable DMA Coalescing on all active ports in the system. You may not gain any energy savings if it
is enabled only on some of the ports in your system.
See Direct Memory Access (DMA) Coalescing
platform, and application settings that will affect your potential energy savings.
Any incoming packet with the TCP PSH flag will trigger an imme-
diate interrupt. The PSH flag is set by the sending device.
Every packet received on the specified ports will trigger an imme-
diate interrupt. Up to 8 ports may be specified.
for a list of supported devices, and information on BIOS,