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Principles of Operation
Figure 4-1 illustrates the approximate location of
each functional unit on the iSBC 432/ 100 Processor
Board; a block diagram of the board is shown in
figure 4-2. The following paragraphs present a brief
description of each functional unit. A circuit analysis
of each unit is also given (beginning with para-
graph 4-11).
4.3 CLOCK GENERATION
Two clocks are generated on the iSBC 432/ 100
board. One clock drives the GDP and all on-board
logic that is synchronized with the processor. The
second clock drives both the 8253 Programmable
Interval Timer (PIT) and the 825 lA Universal Syn-
chronous/ Asynchronous
Receiver /Transmitter
(USART).
GDP operation requires two clock phases, CLKA
and CLKB, that differ by 90 degrees (ref er to figure
4-3). These clock phases are generated from the out-
put of a crystal oscillator and both are buffered by
high-current line drivers and resistively terminated.
The second clock is derived from a 14. 7456 MHz
crystal attached to an 8284 clock generator. The
divide-by-six output of the 8284 (2.4576 MHz)
provides the 8251A master clock. This frequency is
further divided by two, generating a 1.2288 MHz
clock for the 8253 timers. The 8253 is programmed to
provide the baud rate for the 825 lA.
iSBC 432/100
4.4 iAPX 432 PROCESSOR
The GDP is composed of two VLSI devices: the
43201 and the 43202. These devices are inter-
connected by means of a dedicated 16-bit bus and
three dedicated status signals. Both devices operate
with the same clock and are connected to a common
16-bit multiplexed address/ data bus. The two clock
phases (CLKA and CLKB) control the 43201/43202
timing. The GDP interfaces with external logic by
means of the 16-bit multiplexed address/data bus
(the packet bus or ACD bus). All external logic tim-
ing is synchronous with clock transitions. Most input
signals are sampled by the processor on the rising
edge of CLKA; inputs on the ACD bus are sampled
on the falling edge of CLKA. Most CPU outputs
may be sampled by external logic on the falling edge
of CLKA.
Data read and write addressing information is output
on the ACD bus by the GDP in two 16-bit informa-
tion cycles. The first double-byte output contains an
8-bit operation code and the least significant 8 bits of
the address. The next double-byte contains the most
significant 16 bits of the address. The 8-bit operation
code contains an operation specifier
(1
bit), an access
specifier (1 bit), and a length specifier (3 bits). The
operation specifier indicates whether the procesor is
executing a read or write operation. The access
specifier indicates the issuance of a local address
versus a physical memory address. Finally, the length
specifier indicates the number of data bytes
(1,
2, 4,
6, 8, or 10) affected by the data transfer. During pro-
cessor transfer requests, the external circuitry hand-
shakes with the GDP by means of the ISA and ISB
control signals.
SERIAL
1/0
CONNECTOR
CPU
CLOCK
GENERATOR
I
I
8
43201
83202
i
?
!
RS-232-C
I
!INTERFACE
I
I
I
I
I
iAPX 432 CPU
:
DATA-TRANSF~~~w~~
l
4-2
r--- - __
.1.. _____ - - - - - - - - , - - - - - - - - - - -
_...1 __
------1
;------
:
l
~
:
I
I
I
c
I
:
:
MULTIBUS™ ADDRESS
:
LOCAL
1/0
:
1
GENERATION
:
~
:
:
I
1
1
TIMER
I
:
I
:
AND
------'- ------- - ------------.!.------ - ---- - --- - - - - --
L ----
- - T -
_..J
SERIAL
1/0
I
MULTIBUS™ INTERFACE
MULTIBUS™ INTERFACE CONNECTOR
CLOCK
GENERATOR
Figure 4-1. iSBC 432/ 1 OO™ Processor Board Functional Areas
171820-16
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