Intel iSBC 432/100 Hardware Reference Manual page 20

Processor board
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iSBC 432/100
BCLK/
BREQ/
BPRN/
BUSY/
BPRO/
ADDRESS
WRITE DATA
WRITE COMMAND
WRITEXACK/
READ COMMAND/
READ DATA
READ XACK/
1 acv---..j
I
'aw---1
H
r-
taw
Preparation for Use
I
tt~.J
--------------
~
tas
=7
_J
~1---------____,r(
___ _
l.--1DBY
~
l.:==1Dao
=7
\
STABLE ADDRESS
~
(
=7
J
~TABLE
DATA
x
T
IAS· IDS
.____r- _ _ _ _
--1____,i:==
'AH· 'DHW
\w •
......_~~~~~tcMDw~~~~~-----4~~/r-----------
\'--__ __;. ____________ --'7
IACKWT\
u
__J
k-
txAH
STABLE DATA
IDXL~
r-
- - - 1
I
L.DHR
*
CBRQ/ timing not shown relative to other bus signals other than BCLK/.
Figure 2-1. Bus Exchange Timing (Master Mode)
171820-2
2-9

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