Intel iSBC 432/100 Hardware Reference Manual page 43

Principles of Operation
iSBC 432/100
15 14 13 12 10 9 8 7 0
ADDRo.7
.__-----1.-
TRANSFER LENGTH
000· 1 BYTE
001 • 2 BYTES
010· 4 BYTES
011 • 6 BYTES
100· 8 BYTES
101 • 10 BYTES
110 ·RESERVED
111 ·RESERVED
" - - - - - - - - - - - - . OPERATION TYPE
0-READ
1-WRITE
" - - - - - - - - - - - - - ACCESS TYPE
0 ·PHYSICAL MEMORY ACCESS
1 ·LOCAL ACCESS
Figure 4-8. Eight-Bit Transfer Specification Opcode.
171820-23
"next" state (recorded in latch A25 at 4C4), a 3-bit
command code, and the processor ISB signal. The
inputs to the PLA include the 4-bit current state
(from latch A25), the processor ISA signal, the
CNT 1 signal from the transfer counter, the odd/ even
address flag (least significant address bit), and the
operation type (read/write).
In addition, three synchronized signals are input to
the PLA: the Multibus transfer acknowledge signal
(XACK/), the interprocessor communication request
(from flip-flop A23 at 4C6), and the processor
"access stop" request (from flip-flop A26 at 4C6).
A transition from one PLA state to another state
occurs as the result of an input signal change. The
following twelve input signals (16 bits) completely
control state transitions:
Input
Signal
STATE
ISA
IPCRQ
Description
4-bit current state number (from A25 at 4C4)
Processor generated data transfer request
signal
Interprocessor communication request
(from A23 at 4C6)
BXACK Synchronized Muitibus XACK sigr1ai
STOPRQ Processor "access stop" request (from A26
at4C6)
PINIT I Processor initialization signal
CNT1 Last-byte transfer indicator
AO Odd/even address flag (least significant
address bit)
WRITE Processor write transfer indicator
4-10
During each state transition clock cycle, one of the
following eight commands (specified by the 3-bit
command code) is executed:
Command Command
Description
Code Name
0
2
3
4
5
6
7
COUNT
CLRIPC
LDLOW
LDHIGH
Increments the transfer
counter.
Clears pending interprocessor
communication requests.
Latches the least-significant 8
bits of the initial Multibus
address in the address
counters (A33 and A34).
Latches the most-significant 12
bits of the initial Multibus
address into the address
counters (A17, A31, and A32).
UNLOCK Unlocks the Multibus bus
(overrides the bus lock) at the
completion of a processor-
requested data transfer.
STOPPED Signals that processor
Multibus accesses have been
stopped.
NOOP No operation.
Not used.
The state diagram for the data transfer state machine
is given in figure 4-9. To illustrate actual state
machine operation, the following paragraphs
describe a four byte memory write operation on an
even byte boundary (in the 16-bit mode). While
reading the discussion, follow the state transitions as
depicted in figure 4-9.