Table of Contents
Advertisement
Basic Operation and Features
in the FPGA if 8 bit output is selected. The digital shifter selects the most significant 8 bits out of
the 10 bits for the A504
In the next step, different data flows occur:
• In the A504
• In the A503
• In the A501
The 8 Bit video data per pixel is transmitted from the camera to the frame grabber using a Camera
Link transmission format (see section
For optimal digitization, gain and offset are programmable via a serial port.
clear
Control
Logic
10 x 10 Bit
Figure 3-1: A500
3-2
PRELIMINARY
and A501
k,
k,
A503
, the data is formatted to be output in 10 parallel data streams (10 taps).
k
, the data is formatted to be output in 8 parallel data streams (8 taps)
k
the data is formatted to be output in 2 parallel data streams (2 taps).
k,
Pixel
Memory
CMOS-Sensor
1
2
3
1
2
3
4
1024
Ref
10
10
10
10
Digital-Output Sensor
Sensor Architecture
k
.
k
2.5
for details).
10
11
12
Digital 128 Stage Shift Register
128 Cells
20
21
1280
10 x 10 x 128
Basler A500
k
Advertisement
Table of Contents
Troubleshooting
