Basler A500k User Manual page 37

ExSync
Signal
Frame
Valid
Line
Valid
Pixel
Clock
(67.58 MHz)
D_0
Pixel Data
(8 bits)
D_1
Pixel Data
(8 bits)
D_2
Pixel Data
(8 bits)
D_9
Pixel Data
(8 bits)
This diagram assumes that the area of interest feature is not being used. With the area of interest feature enabled,
the number of pixels transferred could be smaller.
Figure 2-8: 8 Bit Output Mode with Edge or Level-controlled Exposure for the A504k
k
Basler A500
PRELIMINARY
min. 3 µs
0.06 µs
0.015 µs
Line 1
1 11 1261 1271
2 12 1262 1272
3 13 1263 1273
10 20 1270 1280
2000 µs
1.89 µs
Line 2
1.95 µs
1
1271
2
1272
3 1273
10 1280
Camera Interface
0 µs
Line 1024
1 11 1261 1271
2 12 1262 1272
3 13 1263 1273
10 20 1270 1280
2-23