Basler A500k User Manual page 41

ExSync
Signal
Frame
Valid
Line
Valid
Pixel
Clock
(67.58 MHz)
D_0
Pixel Data
(8 bits)
D_1
Pixel Data
(8 bits)
D_2
Pixel Data
(8 bits)
D_7
Pixel Data
(8 bits)
This diagram assumes that the area of interest feature is not being used. With the area of interest feature enabled,
the number of pixels transferred could be smaller.
Figure 2-10: 8 Bit Output Mode with Edge or Level-controlled Exposure for the A503k
k
Basler A500
PRELIMINARY
min. 3 µs
0.06 µs
0.015 µs
Line 1
1 9 1265 1273
2 10 1266 1274
3 11 1267 1275
8 16 1272 1280
2485 µs
2.37 µs
Line 2
2.43 µs
1
1273
2
1274
3 1275
8 1280
Camera Interface
0 µs
Line 1024
1 9 1265 1273
2 10 1266 1274
3 11 1267 1275
8 16 1272 1280
2-27