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A
S
BOUT THE
ERVER
[1.3.195] GPIO List (Continued)
I
P
#
P
N
TEM
IN
IN
AME
72
AM36
TACH7_GPIO71
73
E38
GPIO72
74
B33
GPIO73
SML1ALERT_N_PCH
75
J33
HOT_N_GPIO74
IO
P
OWER
PU/PD
R
ECOMMENDATIONS
TYPE
WELL
(
REFERENCE DESIGN
"In Core Power Well.
Muxed with TACH7.
Defaults to GPI. If not
I
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
"In Suspend Power Well.
Unmuxed. Defaults to
O
P3V3_AUX
PU
Native. If not used, require
a weak pull-up (8.2kohm to
10kohm) to VccSus3_3"
"In Suspend Power Well.
Unmuxed. Defaults to GPI.
I
P3V3_AUX
PU
If not used, require a weak
pull-up (8.2kohm to
10kohm) to VccSus3_3"
"In Suspend Power Well.
Muxed with SML1ALERT#/
O
P3V3_AUX
PU
PCHHOT#. Defaults to
Native. "
V
A
ENDOR
LTERNATE
U
SED
FUNCTION
FUNCTION
)
(D
)
EFAULT
TACH7
GPI
(GPI)
GPIO72
Native
(Native)
GPIO73
GPI
(GPI)
SML1ALER
T_N\PCHH
GPO
OT_N
(Native)
1-73
N
STATE
ET
NET
AFTER
CONNECT
NAME
RESET
TO
Connect
to PCIE
PCIE_SL
slot6 and
OT6_PRE
high
P3V3
PU to
SENT_N
P3V3 via
10K
i350, and
Pull up
FM_LOM_
P3V3_A
P3V3
DEV_OFF
high
UX via
_AUX
_N
10Kohm
(empty)
connect
JTAG_PB
to PLD
P3V3
G_PLD_T
high
via a
_AUX
MS
0hm
BMC and
FM_SSB_I
pull up
BMC_THE
P3V3
high
P3V3_A
RMTRIP_
_AUX
UX via
N
10Kohm
GPIO L
IST
PCIE
slot6
pres-
ent pin
i350
LAN
device
control
Reserv
ed for
JTAG
for
CPLD
on-line
update
PCH
HOT
indicate
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