Caterr# - QUANTA W Mainboard Series S210-MBT2W Technical Manual

A S
BOUT THE ERVER
Note:
[1.3.219] A delay circuit (10ms +/- 25%, based on the fact
that the SGPIO bus is running at 100Mhz/4 and one shift
cycle take 80 clocks) must be incorporated on the
THERMTRIP_N signal before the signal is connected to the
Patsburg SSB THERMTRIP_N pin. This is required so that
the ASPEED AST2300 controller can sample the event
before the system shuts down
[1.3.220] THERMTRIP# Timing Diagram

[1.3.221] CATERR#

[1.3.222] The CATERR# signal from the SNB-EP / IVB-EP Pro-
cessor signals that there has been a catastrophic error. Two
types of issues may be signaled by CATERR#. One type is a
warning and is indicated by a 16 BCLK period pulse on the
CATERR# signal. The other is the static critical error which is
indicated by a continuously asserted level on the signal. The
ASPEED AST2300 BMC only logs the static Critical Error
events and it ignores the warnings indicated by the pulse. An
error on the SNB-EP / IVB-EP Processor is immediately com-
municated to the Patsburg SSB, for notification and SMI han-
dler generation. The CATERR# signal must be interconnected
between processors without any logic in its path in order to
achieve the tight timing requirements of this signal. The
CATERR# signal must be isolated and voltage translated
before being connected to the Patsburg Server South Bridge
and the ASPEED AST2300 BMC.
[1.3.223] The ability to capture this signal at the ASPEED
AST2300 BMC requires that the input filters on the GPIO be
turned off and the GPIO placed into event capture mode.
[1.3.224] The CATERR# and ERR [1] # signals must be buff-
ered through individual 400usec delay circuits before being
connected to their corresponding Patsburg SSB GPIO signals.
This is due to an erratum on the Sandy Bridge-EP processor
where an MCA event and SMI handler execution race condition
might occur. This is a platform requirement. Refer to the Rom-
ley Common Core System GPIO architecture.
1-79
CATERR#