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A
S
BOUT THE
ERVER
[1.3.195] GPIO List (Continued)
I
P
#
P
N
TEM
IN
IN
AME
19
B29
GPIO18
20
A25
SATA1GP_GPIO19
21
F24
GPIO20_SMI_N
22
J24
SATA0GP_GPIO21
23
F27
SCLOCK_GPIO22
24
AR37
LDRQ1_N_GPIO23
IO
P
OWER
PU/PD
R
ECOMMENDATIONS
TYPE
WELL
(
REFERENCE DESIGN
"In Main Power Well.
I/O
P1V1_SSB
NA
Unmuxed. Defaults to
GPO. "
"In Main Power Well.
Muxed with SATA1GP.
Defaults to GPI. If not
O
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
"In Main Power Well.
O
P1V1_SSB
PU
Muxed with SMI#. Defaults
to SMI#. "
"In Main Power Well.
Muxed with SATA0GP.
Defaults to GPI. If not
I
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
"In Main Power Well.
Muxed with SCLOCK.
Defaults to GPI. If not
O
P1V1_SSB
PU
used, require a weak pull-
up (8.2kohm to 10kohm) to
Vcc3_3"
"In Main Power Well.
I
P1V1_SSB
NA
Muxed with LDRQ1#.
Defaults to LDRQ1#. "
V
A
ENDOR
LTERNATE
U
SED
FUNCTION
FUNCTION
)
(D
)
EFAULT
GPIO18
GPO
(GPO)
SATA1GP
GPO
(GPI)
SMI_N
GPO
(GPO)
SATA0GP
GPI
(GPI)
SCLOCK
GPO
(GPI)
LDRQ1_N
GPI
(GPI)
1-62
N
STATE
ET
NET
AFTER
CONNECT
NAME
RESET
TO
TP_SSB_
N/A
NC
GPIO18
connect
to WP
pin of
SPI
FM_BIOS
BIOS
_SPI_WP
high
P3V3
and pull
_N
up P3V3
via
4.75Koh
m
BMC and
FM_SMI_
pull up
P3V3
ACTIVE_
high
P3V3 via
N
4.7Kohm
Connect
to PCIE
PCIE_SL
slot1 and
OT1_PRE
N/A
P3V3
PU to
SENT_N
P3V3 via
10K
connect
to pin1 of
J1H1 via
SGPIO_S
49.9 ohm
ATA_CLO
high
P3V3
and pull
CK_R
up P3V3
via
2.0Kohm
PU_LPC_
pull 10k
N/A
P3V3
LDRQ_N
to P3V3
GPIO L
IST
BIOS
SPI
flash
write
pro-
tected
SMI
signal
PCIE
slot1
pres-
ent pin
SGPIO
CLOCK
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