Lpc Bus - QUANTA W Mainboard Series S210-MBT2W Technical Manual

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BOUT THE ERVER

[1.3.42] LPC Bus

[1.3.43] The Patsburg SSB implements a Low Pin Count (LPC)
interface as described in the Low Pin Count Interface Specifica-
tion, Revision 1.1. The LPC interface consists of a 4-bit data
bus, a control frame and a clock input. The LPC interface sup-
ports only 8-bit I/O read and write cycles. The LPC interface
also includes sideband signal SERIRQ and SMI. The Patsburg
SSB LPC interface on S210-MBT2W supports the ASPEED
AST2300 BMC as well as the TPM/TCM security connector.
[1.3.44] Trusted Platform Mod-
ule
[1.3.45] TPM Module
[1.3.46] Trusted Platform Module (TPM) is a chip that provides
platform security functions such as hash, encryption and secure
storage. The Romley platform should support a TCG Client
specification 1.2 compliant TPM device in order to support the
LT-SX/TXT feature. BIOS should implement support for TPM
1.2 device appropriately.
[1.3.47] TPM Clock Requirement
[1.3.48] The 33Mhz clock going to Patsburg needs to also be
connected to the TPM clock in order to comply with security
requirements. This ensures that malicious code does not by-
pass security mechanisms and attempt to disable the TPM by
shutting off the 33Mhz clock. If the 33Mhz TPM clock is some-
how shut off it will disable Patsburg, which will halt the system,
thus preventing any further security intrusion.
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