ZiLOG System 8000 Hardware Reference Manual page 161

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4.9.4. Break Registers: Two 8-bit hardware registers, the
System Break Register (SBR) and the Normal Break Register
(NBR), are accessable as I/O ports on the CPU board. During
any memory reference, the 16-bit logical address offset gen-
erated by the CPU is compared to the break value given by
the contents 'of either the SBR or theNBR. The SBR is
referenced for the break value if the segment number is zero
or one, and the NBR if it is otherwise. If the MMU confi-
guration specifies separation of code, data, and stack
areas, and the CPU status indicates a nonprogram reference
(status 10xx), then the result of this comparison selects
between data and stack references. If the logical address
offset is less than the break value, the current reference
is for data (MMU M2 is enabled); otherwise, it is a stack
reference (MMU M3 is enabled). The following paragraphs
describe the possible configurations of operating systems
(OS) and user programs (USER).
Nonsegmented
as,
Nonsegmented USER
This configuration is intended to run operating systems in
memory segment 0 and user programs in any segment, 2 to 63.
(Segment 63 is recommended for running user programs.)
For operating systems executing in this configuration, MMU
M1 (code) is enabled for program references indicated by a
CPU status code 11xx, an instruction space
access~
For
memory references other than program references, the logical
address offset generated by the CPU is compared against the
contents of the SBR, if the segment number is zero or one;
however, if the
se~ment
number is 2 - 63, the comparison is
made against the contents of the NBR. If the result of the
comparison is less than zero, the select logic
enabll~s
MMU
M2 (data); otherwise, MMU M3 (stack) is enabled.Addition-
ally, logic on the CPU board detects memory references made
to segment 0,1· while the CPU is in normal operation mode.
This logic generates a segment trap violation to the Z8001
CPU, disables the three MMUs, and asserts a suppress signal
that prohibits main memory references.
If the operating system, or any part thereof, executes in
segment mode, the separation of code, data, and stack
spac~s
still applies.
NOTE
The separation between data and stack spaces is
based on the contents of the SBR for segment 0,
and the NBR for references to all other segments.
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