ZiLOG System 8000 Hardware Reference Manual page 156

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4.7.3. ECC Memory Error NMI:
A non-maskable interrupt will
be sent to the CPU when a double-bit non-correctable ECC
memory "error is flagged by the ECC Controller, and when the
CLEAR ECC ERROR-bit of the System Configuration Register
(SCR) is set to enable an ECC NMI. The error bit is ini-
tially cleared at the SCR during a system reset or power-up.
4.7.4. NMI Identifier: When a non-maskable interrupt is
detected by the CPU, the subsequent initial instruction
fetch cycle is initiated, but aborted. The program counter
(PC) is not updated, but the system stack pointer is decre-
mented. The next CPU machine
~ycle
is the interrupt ack-
nowledge cycle. This cycle acknowledges the interrupt and
reads a 16-bit IDENTIFIER word (all 16 bits can represent
peripheral device status and ID information) from the device
that generated the interrupt (in this case, an NMI source).
This identifier word, along with the program status informa-
tion, is stored on the system stack and new status informa-
tion is loaded into the PC and FCW (flag and control word
register) .
When the CPU generates an NMI acknowledge status code
(0101), the source of the NMI will be either a manual,
power-fail, or ECC memory error NMI. Dedicated logic on the
CPU board enables a 4-bit error buffer to place a 4-bit NMI
IDENTIFIER on mulitplexed address/data lines ADO to AD3, as
follows:
AD3
o
o
o
AD2
o
o
1
AD1
o
1
o
ADO
1
o
o
SOURCE
Manual NMI
Power-fail NMI
ECC Memory Error NMI
Bits AD4 to AD15 are "don't care" bits in an NMI acknowledge
identifier word if the NMI source is anyone of the three
listed sources of NMI in the System 8000. If the NMI source
is external to the CPU and not one of the three listed
sources of the NMI, the NMI buffer will remain off and the
16-bit identifier word will be read from the system bus.
4.8. Vectored Interrupts
When the CPU acknowledges an interrupt from a peripheral
device, it reads a 16-bit identifer word to identify the
source of the interrupt. In vectored interrupts, the iden-
tifer is also used by the CPU as a pointer to select a par-
ticular interrupt service routine associated with the peri-
pheral that was the source of the interrupt.
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