ZiLOG System 8000 Hardware Reference Manual page 157

HRM
Zilog
HRM
The System 8000 CPU can configure all PIO (Parallel 110 Con-
troller), eTC (Counter/Timer
C~rcui
t), and SID (Sertal I/O
Controller) peripheral devices for vectored interrupt opera-
tion. The" interrupt vectors associated with
thesE~
peri-
pherals can be loaded at any time since these devices are
initialized with their interrupts disabled (masked).
NOTE
It is recommended that vectored interrupts be dis-
abled by the CPU until all peripherals on the Sys-
tem 8000 CPU have been properly initialized
because of the vectored interrupt daisy-chain.
Since there are several Z80B peripheral devices on the CPU
board, an interrupt daisy-chain is used to prioritize the
devices and to accelerate their interrupt request time.
Each Z80B device contains two lines that function as links
in the daisy-chain: lEI, Interrupt Enable In (INPUT, active
high) and lEO, Interrupt Enable Out (OUTPUT, active high).
The Z80B peripherals on the CPU board are prioritized in a
daisy-chain as indicated in Table 4-26.
Figure 4-15 illus-
trates the daisy-chain configuration.
4-64
Zi10g
4-64