ZiLOG System 8000 Hardware Reference Manual page 147

HRM 2ilog
SIGNAL
DEFINITION
Track Number TR2\ TR1\
0
High
Low
1 Low
High
2
Low Low
3
High High
HRM
SLG\
SL4\,SL2\,SL1\
Allows selection of tape drive designated
by unit select codes: SL4\, SL2\, SL1\.
These form the unit (drive) select code
listed below:
Drive Selected
o
1
2
3
SL4\
H
H
H
L
SL2\
H
L
L
H
SL1\
L
H
L
H
4.5.5. Tape Controller Operation:
To start a tape opera-
tion, the host CPU reads the high-order byte of the
controller's interrupt vector to see if BUSY is set. If the
busy bit is set, the controller is still executing the last
command. If the controller is not busy, the host
initial~
izes the interface registers and then writes a non-zero com-
mand in" the controlleF's command register. The flowchart in
Figure 4-9 shows the steps taken by the host.
The controller normally loops while it waits for a non-zero
command from the host. When the controller receives a com-
mand, it resets the interrupt-pending bit (IP) in the master
interrupt control register. The controller sets the busy
bit in the upper byte of the interrupt vector register to
inform the host that it is busy with the current command.
However, before the controller processes the command, it
checks the validity of the command.
After processing the command, the controller resets the com-
mand register and sets the IP bit. Next, the controller
sends an interrupt to the host and waits for an acknowledge-
ment, the controller sends its interrupt vector in response
to the acknowledgement. An upper byte of zero means that no
errors occurred. The controller also sets the interrupt-
under-service bit (IUS).
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