Read Direct, Internal Basic Processor; Read Direct, Interrupt Control (Mode 1; Read Direct Mode 9 Status Word - Xerox 550 Reference Manual

loaded into register R. Although the Q address field permits
any of 32 addresses to be specifi ed, only the following may
be used:
Q
Address
X'lD'
X'lE'
Contents
{
(Bits 0-13) - Reserved
(Bits 14-31) - "Branch from" Program
Counter
{
(Bits 0-7) - Reserved
(Bits 8-31) - Load Device Address
All other Q addresses from X'OO' - X'lF' are reserved.
Affected: (R)
EW-R
READ DIRECT, INTERRUPT CONTROL (MODE 1)
The following configuration of RD is used to control the
sensing of the various states of the individual interrupt
levels within the basic processor interrupt system:
Bits 28 through 3·1 of the effective address specify the iden-
tification number of the group of interrupt levels to be con-
trolled by the READ DIRECT instruction.
Thp R fiplrJ of thp RD instruction specifies a general register
that will contain the bits sensed from the individual inter-
rupt levels within a specified group. For external interrupt
groups, bit position 16 of register R contains the appropriate
indi cator bit for the highest priority (lowest number) inter-
rupt level within the group and bit position 31 of register R
contains the indi cator bit for the lowest priority interrupt
level within the group. For assignments in Group X'O', see
Table 11. Each interrupt level in the designated group is
sensed according to the function code specified by bits 21
through 23 of the effective address of RD. The codes and
their associated functions are as follows:
Code Function
001 Read Armed or Waiting State. Set to 1 the bits in
the selected register which correspond to interrupt
levels in this group that are in either the armed or
the waiting state. Reset all other bits to zero.
010
100
Read Waiting or Active State. Set to 1 the bits
in the selected register which correspond to each
interrupt level in this group that is in either the
waiting or the active state. Reset all other bits
to zero.
Read Enabled. Set to 1 the bits in the selected
register which correspond to each interrupt level
in this group which is enabled. Reset all other
bits to zero.
READ DIRECT (MODE 9)
READ CONFIGURATION CONTROL PANEL
The mode 9 instruction reads the state of the Configuration
Control Panel for the addressed cluster or unit. Physi cal
addresses are assigned at the time of system configuration.
The returned status to Register R is shown in Tables 11 and 12.
Table 11. Read Direct Mode 9 Status Word
RD Status Word
Bit No.
Basic Processor Cluster
Memory Unit 1
00 System Select
System Select
01 Clock Select Clock Select
02 Processor CI uster Address 22
Unit No. 22
03 Processor Cluster Address 21
Unit No. 21
04
Processor Cluster Address 2 0 Unit No. 2 0
05
BP Enable
Port Enab I e 1
06
MIOP Enable
Port Enab Ie 2
07 DIO Enable Port Enable 3
Control Instructions 105