Glossary Of Symbolic Terms - Xerox 550 Reference Manual

APPENDIX B. GLOSSARY OF SYMBOLIC TERMS
Term
()
n
u
@
CC
CI
EB
EBl
ED
EDl
EH
Meaning
Contents of.
AND (logical product, where 0
n
0 = 0,
o
n
1 = 0, 1
n
0 = 0, and 1
n
1 = 1).
OR (logical inclusive OR, where 0 u 0 = 0,
Ou 1 =1,1 uO=l, and 1 u 1 =1).
EOR (logical exclusive OR, where
o
@
0 = 0, 0
@
1 = 1, 1
@
0 = 1,
and 1 @ 1 = 0).
Fixed-point arithmetic trap mask-bit posi-
tion 11 of PSWs. If set (=1), basic processor
traps to location X ' 43
1 after executing an
instruction causing fixed-point overflow; if
not set, basic processor does not trap.
Condition code - 4-bit value (bit positions
labeled CC1, CC2, CC3, and CC4), estab-
lished as part of the execution of most
i nstructi ons.
Counter interrupt group inhibit - bit posi-
tion 37 of PSWs. If set (=1), all interrupt
levels within this group are inhibited.
Effective byte - 8-bit contents of effective
byte location (EBl).
Effective byte location - byte location
pointed to by effective virtual address of an
i nstructi on for byte operati on.
Effective doubleword - 64-bit contents of
effective doubleword location (EDl).
Effective doubleword location - doubleword
location pointed to by effective virtual ad-
dress of an instruction for a doubleword opera-
tion. If odd-numbered word location is
spec ifi ed, low-order bit of effecti ve address
field (bit position 31) is automatically forced
to O. Hence, odd-numbered word address
(referring to middle of doubleword) desig-
nates same doub!e\AJord as even-num'bered v{ord
address when used for a doubleword operation.
Effective halfword - 16-bit contents of ef-
fective halfword location, or (EHl).
174 Appendix B
Term
EHl
EI
ESA
EVA
EW
EWl
FN
FR
FS
FZ
Meaning
Effective halfword location - halfword loca-
tion pointed to by effective virtual address of
an instruction for halfword- operation.
External interrupt group inhibit - bit
position 39 of PSWs.
If set (=1), all
interrupt levels within this group are
inhibited.
Effective source address.
Effective virtual address - virtual address
value obtained as result of indirect address-
ing and/or indexing. This address value is
independent of the program's actual location
in main memory, and is final address value
before memory mapping is performed.
Effective word - 32-bit contents of effective
word location (EWl).
Effective word location - word location
pointed to by effective virtual address of an
instruction for a word operation.
Floating normalize mode control - bit posi-
tion 7 of PSWs. If not set, resul ts of floating-
point additions and subtractions are to be
normalized; if set (=1), results are not
normalized.
Floating round mode control - bit position 4
of PSWs. If set (=1), basic processor rounds
floating-point results. If not set, results are
truncated.
Floating significance mode control - bit posi-
tion
5 of PSWs. If set (=1), basic processor
traps to location X ' 44 1
when more than two
hexadecimal places of postnormalization
shifting are required for a floating-point ad-
dition or subtraction; if not set, no signifi-
cance checking is performed.
Floating zero mode control - bit position 6
of the PSWs. If set (=1), basic processor
traps to location
X'44'
when either charac-
teristic underflow or zero result occurs for
a floating-point multiplication or division;
if not set, characteristic underflow and zero
result are treated as normal conditions.