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Alto Hardware Manual
Section 3: Emulator
26
3.2 Interrupts
The emulator microcode provides 15 channels of vectored interrupts. The microcode implements only a
single level of interrupts; however, a multi-level priority interrupt system may easily be implemented in
software (see below).
Interrupts may be caused in two ways:
microcode
software
This method is used by I/O device microcode.
A
device usually has a dedicated location
in which the CPU program places a word containing ones in the bit positions
corresponding to the channels on which to cause interrupt(s) upon completion of I/O
activity. The emulator is guaranteed to notice an interrupt caused in this way within
one instruction.
This method is used by a CPU program. A program causes interrupts by oRing into
location
ww
one bits corresponding to the channels on which interrupts should occur.
The emulator is
not
guaranteed to notice an interrupt caused in this way until an EIR
instruction is executed.
When an interrupt occurs, further interrupts are disabled and the state of the interrupted CPU program is
contained in ACO-3, CARRY, and PC, which must be saved and restored by the interrupt routine.
Interrupts can occur between instructions or during long instructions, in which case the instruction's
intennediate state is saved in the accumulators and PC is backed up so that the interrupted instruction is
re-executed when the interrupt is dismissed.
If two interrupts are requested simultaneously, the one with the highest-numbered channel will be
serviced first.
The interrupt system uses a number of fixed locations in page 1:
ACTIVE
453B
ww
452B
PCLOC
500B
INTVEC
501B-517B
This word contains ones for the channels on which interrupts are permitted to
occur. Bit
N
is set to one to enable channel
N.
Bit 0 is reserved and should
not be set by any program.
This word contains bits for channels on which interrupts are pending. This·
information is only valid while the interrupt system is enabled.
Bit
conventions are the same as. for ACTIVE. WW is
not
updated when intemlpts
are disabled -- wakeups caused from microcode accumulate in }..rww until
interrupts are enabled.
When an interrupt is initiated, the PC is saved here. If the CPU program allows
nested interrupts, this location must be saved before re-enabling interrupts.
Contains pointers to the service routines for the 15 interrupt channels. The
first word corresponds to channel 15 (bit 15) and the last corresponds to
channel 1 (bit 1).
Channel 15 is permanently assigned to handling main
memory parity errors.
The interrupt system uses four instructions:
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