Mitsubishi 00JCPU User Manual page 433

(b) When using the index register for a 32-bit instruction
The processing target is Zn and Zn+1.
The lower 16 bits correspond to the specified index register number (Zn), and the higher 16 bits correspond to
the specified index register number + 1.
When Z2 is specified in the DMOV instruction, Z2 represents the lower 16 bits and Z3
Example
represents the higher 16 bits. (The most significant bit in a 32-bit structure is a sign bit.)
Figure 9.63 Data transfer with a 32-bit instruction and storage location
Remark
For details and precautions of index modification using the index register, refer to the following.
MELSEC-Q/L Programming Manual (Common Instruction)
DMOV D0 Z2
Processing target:
Z3
Upper 16 bits Lower 16 bits
CHAPTER9 DEVICES
Z2
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