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MASTER
EDMA3TCx
SRIO (Data Access)
SRIO (Descriptor Access)
EMAC
C64x+ Megamodule (MDMA port)
C64x+ Megamodule (CPU Arbitration control
to L2)
C64x+ Megamodule (IDMA channel 1)
5.5
Power-Down Control
The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule. The
power-down controller (PDC) of the C64x+ Megamodule can be used to power down L1P, the cache
control hardware, the CPU, and the entire C64x+ Megamodule. These power-down features can be used
to design systems for lower overall system power requirements. Note that the device does not support
power-down modes for the L2 memory at this time.
5.6
Megamodule Resets
Table 5-6
shows the reset types supported on the device and if the resetting affects the Megamodule
globally or just locally.
RESET TYPE
Power-On
Warm
System
CPU
5.7
Megamodule Revision
The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID
Register (MM_REVID) located at address 0181 2000h. The MM_REVID register is shown in
and described in
Table
used.
Figure 5-5. Megamodule Revision ID Register (MM_REVID) [Hex Address: 0181 2000h]
31
VERSION
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
(1) The C64x+ Megamodule revision is dependent on the silicon revision being used.
Copyright © 2008–2010, Texas Instruments Incorporated
Table 5-5. C6474 Default Master Priorities
DEFAULT MASTER PRIORITIES
(0 = Highest priority,
7 = Lowest priority)
Table 5-6. Megamodule Reset (Global or Local)
GLOBAL RESET
5-7. The C64x+ Megamodule revision is dependant on the silicon revision being
R-3h
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SPRS552F – OCTOBER 2008 – REVISED JULY 2010
0
QUEPRI.PRIQx (EDMA3 register)
0
PER_SET_CNTL.CBA_TRANS_PRI (SRIO
register)
1
PRI_ALLOC.SRIO_CPPI
1
PRI_ALLOC.EMAC
7
MDMAARBE.PRI (C64x+ Megamodule
register)
1
CPUARBU (C64x+ Megamodule register)
0
IDMA1_COUNT (C64x+ Megamodule
register)
Y
Y
Y
N
16 15
:TMS320C6474
TMS320C6474
PRIORITY CONTROL
LOCAL RESET
Y
Y
Y
Y
Figure 5-5
(1)
REVISION
R-n
C64x+ Megamodule
0
63
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