Pll1 And Pll1 Controller - Texas Instruments TMS320C6474 Manual

www.ti.com
7.8

PLL1 and PLL1 Controller

This section provides a description of the PLL1 controller registers. For details on the operation of the PLL
controller module, see the TMS320C6474 DSP Software-Programmable Phase-Locked Loop (PLL)
Controller User's Guide (literature number SPRUG09).
Note: The PLL1 controller registers can only be accessed using the CPU or the emulator.
Not all of the registers documented in the TMS320C6474 DSP Software-Programmable Phase-Locked
Loop (PLL) Controller User's Guide (literature number SPRUG09) are supported on the C6474 device.
Only those registers documented in this section are supported. Furthermore, only the bits within the
registers described here are supported. You should not write to any reserved memory location or change
the value of reserved bits.
The Main and DDR PLLs are controlled by standard PLL Controller peripherals. The PLL Controllers
manage the clock ratios, alignment, and gating for the system clocks to the chip.
block diagram of the PLL Controller, and the two subsequent sections define the clocks and PLL
Controller parameters for each of the two standard PLLs.
The PLL controller logic is responsible for controlling all modes of the PLL through software, in terms
multiply factor within the PLL and post-division for each of the chip-level clocks from the PLL output. The
PLL controller also controls reset propagation through the chip, clock alignment, and test points. The PLL
controller monitors the PLL status and provides an output signal indicating when the PLL is locked.
AV
DD118
SYS_CLK_(PIN)
ALT_CORE_CLK_(PIN)
CORE_CLK_SEL
Copyright © 2008–2010, Texas Instruments Incorporated
Main.PLL Controller
Main PLL
0
xM /1
1
/2
/n
/4
/3
/6
/m
/20
/20
Figure 7-10. PLL Controller Diagram
Submit Documentation Feedback
Product Folder Link(s)
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
. .
. .
. .
. .
. .
. .
. .
. .
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
Figure 7-10 includes a
AIF SERDES 0
x12.5, 10, 4
AIF SERDES 1
x12.5, 10, 4
To L2 and L2 PDCTL
C64x+ Megamodule
Core 0
C64x+ Megamodule
Core 1
C64x+ Megamodule
Core 2
To Trace
Reserved
CHIP_CLK3
To switch fabric
peripherals,
CHIP_CLK6
accelerators
McBSP_CLKS
EMIF_PTV
117