Enhanced Turbo Decoder Coprocessor (Tcp2) - Texas Instruments TMS320C6474 Manual

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7.17 Enhanced Turbo Decoder Coprocessor (TCP2)

7.17.1 TCP2 Device-Specific Information
The C6474 device has a high-performance embedded coprocessor Turbo-Decoder Coprocessor (TCP2)
that significantly speeds up channel-decoding operations on-chip. The TCP2 operating at CPU clock
divided-by-3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo-encoded channels (assuming 6
iterations). The TCP2 implements the max* log-map algorithm and is designed to support all polynomials
and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable
frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping
criteria are also programmable. Communications between the TCP2 and the CPU are carried out through
the EDMA3 controller.
The TCP2 supports:
• Parallel concatenated convolutional turbo decoding using the MAP algorithm
• All turbo code rates greater than or equal to 1/5
• 3GPP and CDMA2000 turbo encoder trellis
• 3GPP and CDMA2000 block sizes in standalone mode
• Larger block sizes in shared processing mode
• Both max log MAP and log MAP decoding
• Sliding windows algorithm with variable reliability and prolog lengths
• The prolog reduction algorithm
• Execution of a minimum and maximum number of iterations
• The SNR stopping criteria algorithm
• The CRC stopping criteria algorithm
For more detailed information on the TCP2, see the TMS320C6474 DSP Turbo-Decoder Coprocessor 2
(TCP2) Reference Guide (literature number SPRUG21).
7.17.2 TCP2 Peripheral Register Description(s)
EDMA BUS HEX ADDRESS RANGE
5000 0000
5000 0004
5000 0008
5000 000C
5000 0010
5000 0014
5000 0018
5000 001C
5000 0020
5000 0024
5000 0028
5000 002C
5000 0030
5000 0034
5000 0038
5000 003C
5000 0040
5000 0044
Copyright © 2008–2010, Texas Instruments Incorporated
Table 7-78. TCP2 Registers
CONFIGURATION BUS HEX
ADDRESS RANGE
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-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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Product Folder Link(s) :TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
ACRONYM REGISTER NAME
TCPIC0 TCP2 Input Configuration Register 0
TCPIC1 TCP2 Input Configuration Register 1
TCPIC2 TCP2 Input Configuration Register 2
TCPIC3 TCP2 Input Configuration Register 3
TCPIC4 TCP2 Input Configuration Register 4
TCPIC5 TCP2 Input Configuration Register 5
TCPIC6 TCP2 Input Configuration Register 6
TCPIC7 TCP2 Input Configuration Register 7
TCPIC8 TCP2 Input Configuration Register 8
TCPIC9 TCP2 Input Configuration Register 9
TCPIC10 TCP2 Input Configuration Register 10
TCPIC11 TCP2 Input Configuration Register 11
TCPIC12 TCP2 Input Configuration Register 12
TCPIC13 TCP2 Input Configuration Register 13
TCPIC14 TCP2 Input Configuration Register 14
TCPIC15 TCP2 Input Configuration Register 15
TCPOUT0 TCP2 Output Parameters Register 0
TCPOUT1 TCP2 Output Parameters Register 1
Peripheral Information and Electrical Specifications
TMS320C6474
169