11.3
Serial Port Control Register (SPCR)
Figure 50.
Serial Port Control Register (SPCR)
31
23
22
FRST
GRST
R/W-0
R/W-0
15
14
DLB
RJUST
R/W-0
R/W-0
7
6
DXENA
†
Reserved
R/W-0
R-0
†
Available only on C621x/C671x DSP and C64x DSP.
Legend: R = Read only; R/W = Read/Write; -n = value after reset
SPRU580C
The serial port is configured via the serial port control register (SPCR) and the
pin control register (PCR). The SPCR contains McBSP status control bits. The
SPCR is shown in Figure 50 and described in Table 22.
Reserved
R-0
21
20
XINTM
R/W-0
13 12
CLKSTP
5
RINTM
R/W-0
19
18
XSYNCERR
XEMPTY
R/W-0
R-0
11 10
R/W-0
4
3
RSYNCERR
RFULL
R/W-0
R-0
Multichannel Buffered Serial Port (McBSP)
26
25
FREE
†
SOFT
R/W-0
17
XRDY
R-0
Reserved
R-0
2
1
RRDY
R-0
Registers
24
†
R/W-0
16
XRST
R/W-0
8
0
RRST
R/W-0
89