C64X+ Megamodule Register Description(S) - Texas Instruments TMS320C6474 Manual

TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Table 5-7. Megamodule Revision ID Register (MM_REVID) Field Descriptions
BIT FIELD VALUE
31:16 VERSION 3H
15:0 REVISION
5.8

C64X+ Megamodule Register Description(s)

In some applications, some specific addresses may need to be read from their physical locations each
time they are accessed (e.g., a status register within FPGA).
The L2 controller offers registers that control whether certain ranges of memory are cacheable and
whether one or more requestors are actually permitted to access these ranges. The registers are referred
to as memory attribute registers (MARs). A list of MARs is provided in
HEX ADDRESS
0180 0000
0180 0004
0180 0008
0180 000C
0180 0010 - 0180 001C
0180 0020
0180 0024
0180 0028
0180 002C
0180 0030 - 0180 003C
0180 0040
0180 0044
0180 0048
0180 004C
0180 0050 - 0180 007C
0180 0080
0180 0084
0180 0088
0180 008C
0180 0090 - 0180 009C
0180 00A0
0180 00A4
0180 00A8
0180 00AC
0180 00B0 - 0180 00BC
0180 00C0
0180 00C4
0180 00C8
0180 00CC
0180 00D0 - 0180 00DC
0180 00E0
0180 00E4
0180 00E8
0180 00EC
64 C64x+ Megamodule
Version of the C64x+ Megamodule implemented on the device. This field is always read as 3h.
Revision of the C64x+ Megamodule version implemented on the device. The C64x+ Megamodule
revision is dependent on the silicon revision being used.
Table 5-8. Megamodule Interrupt Registers
ACRONYM
EVTFLAG0 Event Flag Register 0 (Events [31:0])
EVTFLAG1 Event Flag Register 1
EVTFLAG2 Event Flag Register 2
EVTFLAG3 Event Flag Register 3
- Reserved
EVTSET0 Event Set Register 0 (Events [31:0])
EVTSET1 Event Set Register 1
EVTSET2 Event Set Register 2
EVTSET3 Event Set Register 3
- Reserved
EVTCLR0 Event Clear Register 0 (Events [31:0])
EVTCLR1 Event Clear Register 1
EVTCLR2 Event Clear Register 2
EVTCLR3 Event Clear Register 3
- Reserved
EVTMASK0 Event Mask Register 0 (Events [31:0])
EVTMASK1 Event Mask Register 1
EVTMASK2 Event Mask Register 2
EVTMASK3 Event Mask Register 3
- Reserved
MEVFLAG0 Masked Event Flag Status Register 0 (Events [31:0])
MEVFLAG1 Masked Event Flag Status Register 1
MEVFLAG2 Masked Event Flag Status Register 2
MEVFLAG3 Masked Event Flag Status Register 3
- Reserved
EXPMASK0 Exception Mask Register 0 (Events [31:0])
EXPMASK1 Exception Mask Register 1
EXPMASK2 Exception Mask Register 2
EXPMASK3 Exception Mask Register 3
- Reserved
MEXPFLAG0 Masked Exception Flag Register 0(Events [31:0])
MEXPFLAG1 Masked Exception Flag Register 1
MEXPFLAG2 Masked Exception Flag Register 2
MEXPFLAG3 Masked Exception Flag Register 3
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DESCRIPTION
Table 5-12.
REGISTER NAME
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