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7 Peripheral Information and Electrical Specifications
7.1
Parameter Information
A.
The data sheet provides timing at the device pin. For output analysis, the transmission line and associated parasitics
(vias, multiple nodes, etc.) must also be taken into account. The transmission line delay varies depending on the trace
length. An approximate range for output delays can vary from 176 ps to 2 ns depending on the end product design.
For recommended transmission line lengths, see the appropriate application notes, user's guides, and design guides.
A transmission line delay of 2 ns was used for all output measurements, except the DDR2 which was evaluated using
a 528-ps delay.
B.
This figure represents all outputs, except differential or I2C.
The load capacitance value stated is for characterization and measurement of AC timing signals. This load
capacitance value does not indicate the maximum load the device is capable of driving.
7.1.1 1.8 V Signal Transition Levels
All input and output timing parameters are referenced to 0.9 V for both "0" and "1" logic levels.
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are reference to V
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
Copyright © 2008–2010, Texas Instruments Incorporated
DDR2 Output Test Load
Transmission Line
Z0 = 50 W
4 pf
Output Test Load Excluding DDR2
Transmission Line
Z0 = 50 W
5 pf
Figure 7-1. Test Load Circuit for AC Timing Measurements
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Device
Data Sheet Timing
Reference Point
(A)
Device Pin
Device
Vref = 0.9 V
MAX and V
IL
V
= V MIN (or V MIN)
ref
IH
OH
V
= V MAX (or V MAX)
ref
IL
OL
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
MIN for input clocks.
IH
75
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