Texas Instruments TMS320C6474 Manual page 131

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7.9.1.2 PLL2 Controller Operating Modes
Unlike the PLL1 controller which can operate in by_pass and _PLL mode, the PLL2 controller only
operates in PLL mode. In this mode, SYSREFCLK is generated outside the PLL2 controller by dividing the
output by two.
The PLL2 controller is affected by power-on reset and warm reset. During these resets, the PLL2
controller registers get reset to their default values. The internal clocks of the PLL2 controller are also
affected as described in
PLL2 is only unlocked during the power-up sequence (see
the time the RESETSTAT pin goes high. It does not lose lock during any of the other resets.
7.9.2 PLL2 Controller Input and Output Electrical Data/Timing
(see Figure 7-22)
NO.
1 t Cycle time, DDRREFCLK(N|P)
c(DDRREFCLK)
2 t Pulse duration, DDRREFCLK(N|P) high
w(DDRREFCLKH)
3 t Pulse duration, DDRREFCLK(N|P) low
w(DDRREFCLKL)
4 t Transition time, DDRREFCLK(N|P)
t(DDRREFCLK)
5 t Period jitter (peak-to-peak), DDRREFCLK(N|P)
j(DDRREFCLK)
(1) C=1/DDRREFCLK(N|P)
DDRREFCLK(N|P)
Copyright © 2008–2010, Texas Instruments Incorporated
Section 7.7, Reset Controller.
Table 7-36. Timing Requirements for DDRREFCLK(N|P)
PARAMETERS
5
Figure 7-22. DDRREFCLK(N|P) Timing
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SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Section 7.7, Reset Controller) and is locked by
1
2
3
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
(1)
MIN MAX UNIT
15 25 ns
0.4C ns
0.4C ns
50 1300 ps
0.02 x ps
t
c(DDRREFCLK)
4
4
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