General Purpose Input/Output (Gpio) - Texas Instruments TMS320C6474 Manual

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7.19 General Purpose Input/Output (GPIO)

On the C6474 device, the GPIO peripheral pins GP[11:0] are used to latch configuration pins. These pins
are sampled at power-on reset and are functional as GPIO pins the remainder of the time. For more
detailed information on device/peripheral configuration and the C6474 device pin muxing, see
Device Configuration.
7.19.1 GPIO Peripheral Register Description(s)
HEX ADDRESS
02B0 0008
02B0 000C
02B0 0010
02B0 0014
02B0 0018
02B0 001C
02B0 0020
02B0 0024
02B0 0028
02B0 002C
02B0 0030
02B0 008C
02B0 0090 - 02B0 00FF
02B0 0100 - 02B0 3FFF
7.19.2 GPIO Electrical Data/Timing
(see Figure 7-44)
NO.
1 t Pulse duration, GPIx high
w(GPIH)
2 t Pulse duration, GPIx low
w(GPIL)
(1) C = 1/CPU CLK frequency, in ns.
Table 7-83. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 7-44)
NO.
1 t Pulse duration, GPOx high
w(GPOH)
2 t Pulse duration, GPOx low
w(GPOL)
(1) C = 1/CPU CLK frequency, in ns.
GPIx
GPOx
Copyright © 2008–2010, Texas Instruments Incorporated
Table 7-81. GPIO Registers
ACRONYM
BINTEN GPIO Interrupt per Bank Enable Register
- Reserved
DIR GPIO Direction Register
OUT_DATA GPIO Output Data Register
SET_DATA GPIO Set Data Register
CLR_DATA GPIO Clear Data Register
IN_DATA GPIO Input Data Register
SET_RIS_TRIG GPIO Set Rising Edge Interrupt Register
CLR_RIS_TRIG GPIO Clear Rising Edge Interrupt Register
SET_FAL_TRIG GPIO Set Falling Edge Interrupt Register
CLR_FAL_TRIG GPIO Clear Falling Edge Interrupt Register
- Reserved
- Reserved
- Reserved
Table 7-82. Timing Requirements for GPIO Inputs
PARAMETER
PARAMETER
2
1
Figure 7-44. GPIO Timing
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Product Folder Link(s)
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
REGISTER NAME
(1)
4
3
Peripheral Information and Electrical Specifications
:TMS320C6474
TMS320C6474
Section 3,
MIN MAX UNIT
12C - 3 ns
12C - 3 ns
(1)
MIN MAX UNIT
36C - 8 ns
36C - 8 ns
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