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TMS320VC5509A Silicon Errata
3.8
Universal Serial Bus (USB) Advisories
Advisory USB_2
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
Advisory USB_5
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
Advisory USB_6
Revision(s) Affected:
Details:
Assembler Notification: None
Workaround:
CPU Might Miss Back-to-Back USB Interrupts When CPU Speed is Less Than or
1.0 and 1.1
When the CPU operates with a clock less than or equal to half the USB module clock,
back-to-back USB interrupts might be missed by the CPU. Back-to-back interrupts occur when
multiple endpoints are active simultaneously or when SOF or SETUP events occur with one
endpoint. The USB module needs to operate at 48 MHz, so the CPU needs to operate at a
clock speed greater than 24 MHz.
Recommended CPU operating frequency is 48 MHz or higher if the USB module is running.
USB Input Cell Does Not Power Down When USB is Placed in IDLE
1.0 and 1.1
USB input cells are always powered unless the oscillator is disabled.
None
CPU Read/Write to USB Module may Return Incorrect Result if the USB Clock is Running
1.0 and 1.1
If the CPU speed is x12 or higher than the USB module clock speed, then the USB RAM and
register read/write will return incorrect result. This is not an issue during normal USB operation
where the USB module clock is 48 MHz. But at power up, the USB DPLL is in bypass div2
mode; hence, the USB module clock is CLKIN/2. As most of the applications program the DSP
PLL first and then all other modules (including USB), this can be a problem if the
(CPU clock):(USB module clock) ratio > 12:1.
Program the USB PLL first to speed up the USB module clock to 48 MHz before programming
the DSP PLL.
Slower Than Recommended Speed (48 MHz)
SPRZ200E
Equal to 24 MHz
22
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