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2.6
Signal Groups Description
AV
DD118
SYSCLKP
SYSCLKN
SYSCLKOUT
CORECLKSEL
ALTCORECLKP
ALTCORECLKN
AV
DD218
TMS
TDO
TDI
TCK
TRST
EMU00
EMU01
EMU02
·
·
·
EMU14
EMU15
EMU16
EMU17
EMU18
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Clock/PLL1
and
PLL Controller
Clock/PLL2
IEEE Standard
1149.1
(JTAG)
Emulation
Figure 2-6. CPU and Peripheral Signals
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Product Folder Link(s)
:TMS320C6474
SPRS552F – OCTOBER 2008 – REVISED JULY 2010
Reset and
Interrupts
Reserved
Control/Status
TMS320C6474
RESETSTAT
RESET
NMI0
NMI1
NMI2
XWRST
RSV
Device Overview
21
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