Sun Microsystems Ultra 20 M2 Service Manual page 124

TABLE B-1
Post Code
CFh
C0h
C1h
C3h
C5h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
B-2 Sun Ultra 20 M2 Workstation Service Manual • January 2007
BIOS Port 80 POST Codes
Description
Test CMOS R/W functionality.
Early chipset initialization:
• Disable shadow RAM.
• Disable L2 cache (socket 7 or below).
• Program basic chipset registers.
Detect memory:
• Auto-detection of DRAM size, type, and ECC.
• Auto-detection of L2 cache (socket 7 or below).
Expand compressed BIOS code to DRAM.
Call chipset hook to copy BIOS back to E000 & F000 shadow RAM.
Expand the Xgroup codes locating in physical address 1000:0.
Reserved.
Initial Superio_Early_Init switch.
Reserved.
1. Blank out screen.
2. Clear CMOS error flag.
Reserved.
1. Clear 8042 interface.
2. Initialize 8042 self-test.
1. Test special keyboard controller for Winbond 977 series Super I/O
chips.
2. Enable keyboard interface.
Reserved.
1. Disable PS/2 mouse interface (optional).
2. Auto-detect ports for keyboard and mouse followed by a port and
interface swap (optional).
3. Reset keyboard for Winbond 977 series Super I/O chips.
Reserved.
Reserved.
Reserved.
Test F000h segment shadow to see whether it is read/write-able or
not. If test fails, keep beeping the speaker.
Reserved.