Compaq AlphaServer GS60 Operation Manual page 141

During the first round of testing each module runs its own self-test and the results are
shown on the ST1 line. The boot processor is then determined (indicated by a B on the
first BPD line). This processor then generates the results of testing to this point ( ).
If one processor on a dual-CPU module fails self-test (ST1), the failing CPU is
displayed as a minus under the node # (for example, – +). The processor failure is also
indicated by the control panel Fault light remaining lit after power-up. If both
processors fail, the module is disconnected from the backplane to prevent faulty system
operation. If a uni-processor (available with KN7CC and KN7CD processor modules)
fails self-test (ST1) in a multiprocessor system, there is no indication of its failure in
the self-test display. The failing processor is logically disconnected from the
backplane and the processor failure is indicated by the control panel Fault light
remaining lit after power-up. In both cases, the module self-test LED will be out.
Next, the processors run a second round of tests using the memory modules. In this
testing the processor that had been designated as boot processor could fail (as shown in
Example 6-3), so the boot processor is again determined. Results are displayed on the
ST2 line ( ).
Finally, the processors run a third round of tests, the multiprocessing tests. Depending
on configuration, there may be some delay at the ST3 line (around 20–60 seconds).
Once again the boot processor is determined. The status of the boot processor and
secondary processors is then displayed on the third BPD line ( ). The I/O adapter
tests are then run.
Results of the I/O adapter self-test are displayed next.
The boot processor next configures memory and displays the configuration. Note that it
is the boot processor determined at ( ) that displays the lines after the third BPD line.
The final line before the console prompt contains the boot processor's SRM console
version number, the date, and the SROM revision ( ).
Each line of the self-test display is described in detail in the following sections of this
chapter.
System Troubleshooting 6-19