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CDM-710G High-Speed Satellite Modem
Clock Modes
10.2 CDI-10-1 Single G.703 Interface
The CDI-10-1 Single G.703 interface has a single port that operates at an E3, T3, or STS-1 data
rate. A port is a Tx/Rx pair. Figure 10-2 shows the interface.
J3
UNBAL
E3/T3/STS - 1
J2
BNC Female 3 Places
J1
EXT Clk
10.2.1
CDI-10-1 Single G.703 Interface Transmit Clocking
For the G.703 interface, the only clock allowed is the SD signal applied to the Tx input. Internal
Clock and Rx Loop-Timed operation do not apply to G.703 applications.
10.2.2
CDI-10-1 Single G.703 Interface Receive Clocking
When the Rx Buffer is disabled, the receive clock is the Rx-Sat. In this mode, ensure the Rx
Buffer is set to minimum to reduce latency.
When the Rx Buffer is enabled, the Rx clock selections are as follows:
Rx-Sat (default)
Tx-Terr
Ext-Clk
Tx
G.703
G.703
UNBAL
E1/T1
UNBAL
E1/T1
Rx
E2/T2
E2/T2
External Clock
Clock
Figure 10-2. CDI-10-1 Single G.703 Interface
Selecting this clock disables the Rx Buffer because the input and output clocks
are both Rx-Sat. Normally, the Rx Buffer is set for minimum when Rx-Sat is
selected.
Uses the clock from the Tx input (SD) to clock out the Rx Buffer. The Tx and
Rx data rates are the same on this interface, so asymmetrical data rates
where Tx ≠ Rx is not permitted. The two data ports are independent, so Port 1
may have a different data rate than Port 2.
Derives a clock from a signal input to the Ext-Clk connector on the
E3/T3/STS-1 Interface Module, not J7 on the modem.
Loopback
Ext
Ext
BAL
BAL
Clock
Single E3/T3/STS -1 Card
10–3
Revision 1
MN-CDM710G
Processor
Processor
Mux /
Mux /
Clk
Demux
Demux
&
Data
PLLs
PLLs
Modem
Interface
μC
Rx
Rx
Buffers
Buffers
Interface
Interface
Loopback
Loopback
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