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Status byte and service request (SRQ)
Service request is controlled by two 8-bit registers; the status byte register and the service
request enable register. Figure 13-3 shows the structure of these registers.
Figure 13-3
Status byte and service
request
Status byte register
The summary messages from the status registers and queues are used to set or clear the appro-
priate bits (B0, B2, B3, B4, B5, and B7) of the status byte register. These summary bits do not
latch, and their states (0 or 1) are solely dependent on the summary messages (0 or 1). For exam-
ple, if the standard event register is read, its register will clear. As a result, its summary message
will reset to 0, which in turn will reset the ESB bit in the status byte register.
Service
* STB?
Request
Serial Poll
Generation
OR
* SRE
* SRE?
Decimal
Weights
Status Summary Messages (6)
RQS
OSB
ESB
MAV
QSB
(B6)
(B7)
(B5)
(B4)
(B3)
MSS
&
&
&
&
OSB
ESB
MAV
QSB
(B7)
(B6)
(B5)
(B4)
(B3)
128
32
16
8
7
5
4
3
(2
)
(2
)
(2
)
(2
)
OSB = Operation Summary Bit
MSS = Master Summary Status
RQS = Request for Service
ESB = Event Summary Bit
MAV = Message Available
QSB = Questionable Summary Bit
EAV = Error Available
MSB = Measurement Summary Bit
Status Structure
13-7
EAV
MSB
Status Byte
(B1)
(B0)
(B2)
Register
&
&
EAV
MSB
Service Request
(B0)
(B1)
(B2)
Enable Register
4
1
2
0
(2
)
(2
)
& = Logical AND
OR = Logical OR
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